/* Nonzero if X is a hard reg that can be used as a base reg.  */#define REG_OK_FOR_BASE_P(X)  REGNO_OK_FOR_BASE_P (REGNO (X))/* Nonzero if X is a hard reg that can be used as an index.  */#define REG_OK_FOR_INDEX_P(X)  REGNO_OK_FOR_INDEX_P (REGNO (X))#define REG_OK_FOR_PRE_POST_P(X)  \  (REGNO (X) < 16 || (unsigned) reg_renumber[REGNO (X)] < 16)#endif/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression   that is a valid memory address for an instruction.   The MODE argument is the machine mode for the MEM expression   that wants to use this address.   The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS.  */#define BASE_REGISTER_RTX_P(X)  \  (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X))#define INDEX_REGISTER_RTX_P(X)  \  (GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X))/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs   used by the macro GO_IF_LEGITIMATE_ADDRESS.  Floating point indices can   only be small constants. */#define GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL)  \do \{										      \  int range;									      \										      \  if (GET_MODE_CLASS (MODE) == MODE_FLOAT)					      \    range = 1024;								      \  else										      \    {										      \      if (INDEX_REGISTER_RTX_P (INDEX))						      \	goto LABEL;								      \      if (GET_MODE_SIZE (MODE) <= 4  &&  GET_CODE (INDEX) == MULT)		      \	{									      \	  rtx xiop0 = XEXP (INDEX, 0);						      \	  rtx xiop1 = XEXP (INDEX, 1);						      \	  if (INDEX_REGISTER_RTX_P (xiop0) &&  power_of_two_operand (xiop1, SImode))  \	    goto LABEL;								      \	  if (INDEX_REGISTER_RTX_P (xiop1) &&  power_of_two_operand (xiop0, SImode))  \	    goto LABEL;								      \	}									      \      range = 4096;								      \    }										      \										      \    if (GET_CODE (INDEX) == CONST_INT && abs (INTVAL (INDEX)) < range)  	      \      goto LABEL;								      \} while (0)/* Jump to LABEL if X is a valid address RTX.  This must also take   REG_OK_STRICT into account when deciding about valid registers, but it uses   the above macros so we are in luck.  Allow REG, REG+REG, REG+INDEX,   INDEX+REG, REG-INDEX, and non floating SYMBOL_REF to the constant pool.   Allow REG-only and AUTINC-REG if handling TImode.  Other symbol refs must   be forced though a static cell to ensure addressability.  */#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL)  \{									\  if (BASE_REGISTER_RTX_P (X))						\    goto LABEL;								\  else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC)	\	   && GET_CODE (XEXP (X, 0)) == REG				\	   && REG_OK_FOR_PRE_POST_P (XEXP (X, 0)))			\    goto LABEL;								\  else if ((MODE) == TImode)						\    ;									\  else if (GET_CODE (X) == PLUS)					\    {									\      rtx xop0 = XEXP(X,0);						\      rtx xop1 = XEXP(X,1);						\									\      if (BASE_REGISTER_RTX_P (xop0))					\	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL);	\      else if (BASE_REGISTER_RTX_P (xop1))				\	GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL);	\    }									\  else if (GET_CODE (X) == MINUS)					\    {									\      rtx xop0 = XEXP (X,0);						\      rtx xop1 = XEXP (X,1);						\									\      if (BASE_REGISTER_RTX_P (xop0))					\	GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL);			\    }									\  else if (GET_MODE_CLASS (MODE) != MODE_FLOAT				\	   && GET_CODE (X) == SYMBOL_REF				\	   && CONSTANT_POOL_ADDRESS_P (X))				\    goto LABEL;								\  else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC)	\	   && GET_CODE (XEXP (X, 0)) == REG				\	   && REG_OK_FOR_PRE_POST_P (XEXP (X, 0)))			\    goto LABEL;								\}/* Try machine-dependent ways of modifying an illegitimate address   to be legitimate.  If we find one, return the new, valid address.   This macro is used in only one place: `memory_address' in explow.c.   OLDX is the address as it was before break_out_memory_refs was called.   In some cases it is useful to look at this to decide what needs to be done.   MODE and WIN are passed so that this macro can use   GO_IF_LEGITIMATE_ADDRESS.   It is always safe for this macro to do nothing.  It exists to recognize   opportunities to optimize the output.   On the ARM, try to convert [REG, #BIGCONST]   into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],   where VALIDCONST == 0 in case of TImode.  */#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN)  \{						        		     \  if (GET_CODE (X) == PLUS)			        		     \    {						        		     \      rtx xop0 = XEXP (X, 0);			        		     \      rtx xop1 = XEXP (X, 1);			        		     \						        		     \      if (BASE_REGISTER_RTX_P (xop0) && GET_CODE (xop1) == CONST_INT)	     \	{					        		     \	  int n = INTVAL (xop1);		        		     \	  int low_n = ((MODE) == TImode ? 0	        		     \		       : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF));	     \	  rtx base_reg = gen_reg_rtx (SImode);	        		     \	  rtx val = force_operand (gen_rtx (PLUS, SImode, xop0,		     \					    gen_rtx (CONST_INT,		     \						     VOIDmode, n - low_n)),  \				   0);					     \          emit_move_insn (base_reg, val);				     \	  (X) = (low_n == 0 ? base_reg					     \		 : gen_rtx (PLUS, SImode, base_reg,			     \			    gen_rtx (CONST_INT, VOIDmode, low_n)));	     \	}								     \      else if (BASE_REGISTER_RTX_P (xop1) && GET_CODE (xop0) == CONST_INT)   \	{								     \	  int n = INTVAL (xop0);					     \	  int low_n = ((MODE) == TImode ? 0				     \		       : n >= 0 ? (n & 0xFFF) : -((-n) & 0xFFF));	     \	  rtx base_reg = gen_reg_rtx (SImode);				     \	  rtx val = force_operand (gen_rtx (PLUS, SImode, xop1,		     \					    gen_rtx (CONST_INT,		     \						     VOIDmode, n - low_n)),  \				   0);					     \	  emit_move_insn (base_reg, val);				     \	  (X) = (low_n == 0 ? base_reg					     \		 : gen_rtx (PLUS, SImode, base_reg,			     \			    gen_rtx (CONST_INT, VOIDmode, low_n)));	     \	}								     \    }									     \  if (memory_address_p (MODE, X))					     \    goto win;								     \}/* Go to LABEL if ADDR (a legitimate address expression)   has an effect that depends on the machine mode it is used for.  */#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)  \{									\  if (GET_CODE(ADDR) == PRE_DEC || GET_CODE(ADDR) == POST_DEC		\      || GET_CODE(ADDR) == PRE_INC || GET_CODE(ADDR) == POST_INC)	\    goto LABEL;								\}/* Specify the machine mode that this machine uses   for the index in the tablejump instruction.  */#define CASE_VECTOR_MODE SImode/* Define this if the tablejump instruction expects the table   to contain offsets from the address of the table.   Do not define this if the table should contain absolute addresses.  *//* #define CASE_VECTOR_PC_RELATIVE *//* Specify the tree operation to be used to convert reals to integers.  */#define IMPLICIT_FIX_EXPR  FIX_ROUND_EXPR/* This is the kind of divide that is easiest to do in the general case.  */#define EASY_DIV_EXPR  TRUNC_DIV_EXPR/* 'char' is signed by default on RISCiX, unsigned on RISCOS.  */#ifdef riscos#define DEFAULT_SIGNED_CHAR  0#else#define DEFAULT_SIGNED_CHAR  1#endif/* Don't cse the address of the function being compiled.  */#define NO_RECURSIVE_FUNCTION_CSE 1/* Max number of bytes we can move from memory to memory   in one reasonably fast instruction.  */#define MOVE_MAX 4/* Define if normal loads of shorter-than-word items from memory clears   the rest of the bigs in the register.   On the ARM, movhi does a garbage extend.  *//* #define BYTE_LOADS_ZERO_EXTEND *//* Define this if zero-extension is slow (more than one real instruction).   On the ARM, it is more than one instruction only if not fetching from   memory.  *//* #define SLOW_ZERO_EXTEND *//* Nonzero if access to memory by bytes is slow and undesirable.  */#define SLOW_BYTE_ACCESS 0/* Immediate shift counts are truncated by the output routines (or was it   the assembler?).  Shift counts in a register are truncated by ARM.  Note   that the native compiler puts too large (> 32) immediate shift counts   into a register and shifts by the register, letting the ARM decide what   to do instead of doing that itself.  */#define SHIFT_COUNT_TRUNCATED 1/* We have the vprintf function.  */#define HAVE_VPRINTF 1/* XX This is not true, is it?  *//* All integers have the same format so truncation is easy.  */#define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC)  1/* Calling from registers is a massive pain.  */#define NO_FUNCTION_CSE 1/* Chars and shorts should be passed as ints.  */#define PROMOTE_PROTOTYPES 1/* The machine modes of pointers and functions */#define Pmode  SImode#define FUNCTION_MODE  Pmode/* The structure type of the machine dependent info field of insns   No uses for this yet.  *//* #define INSN_MACHINE_INFO  struct machine_info  *//* The relative costs of various types of constants.  Note that cse.c defines   REG = 1, SUBREG = 2, any node = (2 + sum of subnodes).  */#define CONST_COSTS(RTX, CODE, OUTER_CODE)  \  case CONST_INT:				\    if (const_ok_for_arm (INTVAL (RTX)))	\      return (2);				\    else					\      return (5);				\						\  case CONST: 					\  case LABEL_REF:				\  case SYMBOL_REF:				\    return (6);					\						\  case CONST_DOUBLE:				\    if (const_double_rtx_ok_for_fpu (RTX))	\      return(2);				\    else					\      return(7);/* Condition code information.  *//* Store in cc_status the expressions   that the condition codes will describe   after execution of an instruction whose pattern is EXP.   Do not alter them if the instruction would not alter the cc's.  *//* On the ARM nothing sets the condition code implicitly---apart from DImode   operations excluding moves---but we have to watch for registers in the   condition code value being clobbered.  This clobbering includes (alas)   function calls.  XXX They could just be considered to clobber regs 0-3 and   10-15 with extra work.  */#define NOTICE_UPDATE_CC(EXP, INSN)  \{									\  if (GET_MODE (EXP) == DImode						\      && GET_CODE (EXP) == SET						\      && GET_CODE (SET_SRC (EXP)) != REG				\      && GET_CODE (SET_SRC (EXP)) != MEM				\      && GET_CODE (SET_SRC (EXP)) != CONST_INT)				\    CC_STATUS_INIT;							\  else if (GET_CODE (EXP) == SET)					\    {									\      rtx dest = SET_DEST (EXP);					\      if (dest == cc0_rtx)						\	{								\	  cc_status.flags = 0;						\	  cc_status.value1 = SET_DEST (EXP);				\	  cc_status.value2 = SET_SRC (EXP);				\	}								\      if (BASE_REGISTER_RTX_P (dest))					\	{								\	  if (cc_status.value1						\	      && reg_overlap_mentioned_p (dest, cc_status.value1))	\	    cc_status.value1 = 0;					\	  if (cc_status.value2						\	      && reg_overlap_mentioned_p (dest, cc_status.value2)) 	\	    cc_status.value2 = 0;				        \	}							        \    }								        \  else if (GET_CODE (INSN) != JUMP_INSN && GET_CODE (EXP) == PARALLEL)	\    {									\      CC_STATUS_INIT;							\    }									\}/* Assembler output control *//* The text to go at the start of the assembler file */#define ASM_FILE_START(STREAM)  \{                                                                             \  extern char *version_string;                                                \                                                                              \  fprintf (STREAM,"@ Generated by gcc %s for ARM/RISCiX\n", version_string);  \  fprintf (STREAM,"rfp\t.req\tr9\n");                                         \  fprintf (STREAM,"fp\t.req\tr11\n");				              \  fprintf (STREAM,"ip\t.req\tr12\n");				              \  fprintf (STREAM,"sp\t.req\tr13\n");				              \  fprintf (STREAM,"lr\t.req\tr14\n");					      \  fprintf (STREAM,"pc\t.req\tr15\n");				              \}#define ASM_APP_ON  ""#define ASM_APP_OFF  ""/* Switch to the text or data segment.  */#define TEXT_SECTION_ASM_OP  ".text"#define DATA_SECTION_ASM_OP  ".data"/* The assembler's names for the registers.  RFP need not always be used as   the Real framepointer; it can also be used as a normal general register.   Note that the name `fp' is horribly misleading since `fp' is in fact only   the argument-and-return-context pointer.  */#define REGISTER_NAMES  \{				                   \  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",  \  "r8","rfp", "sl", "fp", "ip", "sp", "lr", "pc",  \  "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7"   \