?? clockdiv2.sch
字號:
DSCH 2.0b
VERSION 13/10/99 22:06:12
BB(5,5,79,53)
SYM #dreg
BB(25,10,55,35)
TITLE 37 18 #dreg
MODEL 860
PROP
REC(0,0,0,0,r)
VIS 5
PIN(25,15,0.000,0.000)D
PIN(25,25,0.000,0.000)RST
PIN(40,35,0.000,0.000)H
PIN(55,25,4.000,1.000)Q
PIN(55,15,4.000,1.000)nQ
LIG(25,25,30,25)
LIG(25,15,30,15)
LIG(40,35,40,30)
LIG(50,25,55,25)
LIG(50,15,55,15)
LIG(50,30,30,30)
LIG(50,10,50,30)
LIG(30,10,50,10)
LIG(30,30,30,10)
LIG(39,30,40,28)
LIG(40,28,41,30)
VLG module dreg(D,RST,H,Q,nQ);
VLG output Q,nQ;
VLG endmodule
FSYM
SYM #clock1
BB(5,47,20,53)
TITLE 10 50 #clock
MODEL 69
PROP 5.000 5.000
REC(7,48,6,4,r)
VIS 5
PIN(20,50,1.000,50.000)Clock1
LIG(15,50,20,50)
LIG(10,52,8,52)
LIG(14,52,12,52)
LIG(15,53,15,47)
LIG(5,47,5,53)
LIG(10,48,10,52)
LIG(12,52,12,48)
LIG(12,48,10,48)
LIG(8,48,6,48)
LIG(8,52,8,48)
LIG(15,47,5,47)
LIG(15,53,5,53)
FSYM
SYM #light1
BB(73,10,79,24)
TITLE 75 25 #light
MODEL 49
PROP
REC(74,12,4,5,r)
VIS 5
PIN(75,25,0.000,0.000)Clock_Div_2
LIG(78,17,78,12)
LIG(78,12,77,11)
LIG(74,12,74,17)
LIG(77,22,77,19)
LIG(76,22,79,22)
LIG(76,24,78,22)
LIG(77,24,79,22)
LIG(73,19,79,19)
LIG(75,19,75,25)
LIG(73,17,73,19)
LIG(79,17,73,17)
LIG(79,19,79,17)
LIG(75,11,74,12)
LIG(77,11,75,11)
FSYM
SYM #button1
BB(6,31,15,39)
TITLE 10 35 #button
MODEL 59
PROP
REC(7,32,6,6,r)
VIS 5
PIN(15,35,0.000,0.000)Reset
LIG(14,35,15,35)
LIG(6,31,6,39)
LIG(14,31,6,31)
LIG(14,39,14,31)
LIG(6,39,14,39)
LIG(7,32,7,38)
LIG(13,32,7,32)
LIG(13,38,13,32)
LIG(7,38,13,38)
FSYM
LIG(25,15,25,5)
LIG(25,5,55,5)
LIG(55,5,55,15)
LIG(40,35,40,50)
LIG(20,50,40,50)
LIG(55,25,75,25)
LIG(25,25,25,35)
LIG(15,35,25,35)
FFIG C:\Dsch 2.0\Manual\ClockDiv2.sch
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