?? trigger.sch
字號:
Dsch 2.0a - 98
VERSION 28/04/99 22:15:32
BB(16,5,274,150)
SYM #pmos
BB(45,15,65,35)
TITLE 60 20 #pmos
MODEL 902
PROP 2.4 1.2
REC(0,0,0,0)
VIS 1
PIN(65,15,0.000,0)source
PIN(45,25,0.000,0)gate
PIN(65,35,7.000,30)drain
LIG(45,25,51,25)
LIG(53,25,53,25)
LIG(55,19,55,31)
LIG(57,19,57,31)
LIG(65,31,57,31)
LIG(65,35,65,31)
LIG(65,19,57,19)
LIG(65,15,65,19)
VLG pmos pmos(drain,source,gate);
FSYM
SYM #pmos
BB(45,35,65,55)
TITLE 60 40 #pmos
MODEL 902
PROP 2.4 1.2
REC(0,0,0,0)
VIS 1
PIN(65,35,0.000,0)source
PIN(45,45,0.000,0)gate
PIN(65,55,7.000,30)drain
LIG(45,45,51,45)
LIG(53,45,53,45)
LIG(55,39,55,51)
LIG(57,39,57,51)
LIG(65,51,57,51)
LIG(65,55,65,51)
LIG(65,39,57,39)
LIG(65,35,65,39)
VLG pmos pmos(drain,source,gate);
FSYM
SYM #nmos
BB(45,55,65,75)
TITLE 60 60 #nmos
MODEL 901
PROP 2.4 1.2
REC(0,0,0,0)
VIS 1
PIN(65,75,0.000,0)source
PIN(45,65,0.000,0)gate
PIN(65,55,7.000,30)drain
LIG(55,65,45,65)
LIG(55,59,55,71)
LIG(57,59,57,71)
LIG(65,71,57,71)
LIG(65,75,65,71)
LIG(65,59,57,59)
LIG(65,55,65,59)
VLG nmos nmos(drain,source,gate);
FSYM
SYM #nmos
BB(45,75,65,95)
TITLE 60 80 #nmos
MODEL 901
PROP 2.4 1.2
REC(0,0,0,0)
VIS 1
PIN(65,95,0.000,0)source
PIN(45,85,0.000,0)gate
PIN(65,75,7.000,30)drain
LIG(55,85,45,85)
LIG(55,79,55,91)
LIG(57,79,57,91)
LIG(65,91,57,91)
LIG(65,95,65,91)
LIG(65,79,57,79)
LIG(65,75,65,79)
VLG nmos nmos(drain,source,gate);
FSYM
SYM #vss
BB(60,97,70,105)
TITLE 64 102 #vss
MODEL 0
PROP
REC(0,0,0,0)
VIS 0
PIN(65,95,0.000,0).
LIG(65,95,65,100)
LIG(60,100,70,100)
LIG(60,103,62,100)
LIG(62,103,64,100)
LIG(64,103,66,100)
LIG(66,103,68,100)
FSYM
SYM #vdd
BB(60,5,70,15)
TITLE 63 11 #vdd
MODEL 1
PROP
REC(0,0,0,0)
VIS 0
PIN(65,15,0.000,0).
LIG(65,15,65,10)
LIG(65,10,60,10)
LIG(60,10,65,5)
LIG(65,5,70,10)
LIG(70,10,65,10)
FSYM
SYM #button
BB(196,96,205,104)
TITLE 200 100 #button
MODEL 59
PROP
REC(197,97,6,6)
VIS 1
PIN(205,100,0.000,0)Input
LIG(204,100,205,100)
LIG(196,96,196,104)
LIG(204,96,196,96)
LIG(204,104,204,96)
LIG(196,104,204,104)
LIG(197,97,197,103)
LIG(203,97,197,97)
LIG(203,103,203,97)
LIG(197,103,203,103)
FSYM
SYM #pmos
BB(85,35,105,55)
TITLE 90 40 #pmos
MODEL 902
PROP 2.4 1.2
REC(55,145,0,0)
VIS 1
PIN(85,35,0.000,0)source
PIN(95,55,0.000,0)gate
PIN(105,35,7.000,30)drain
LIG(95,55,95,49)
LIG(95,47,95,47)
LIG(89,45,101,45)
LIG(89,43,101,43)
LIG(101,35,101,43)
LIG(105,35,101,35)
LIG(89,35,89,43)
LIG(85,35,89,35)
VLG pmos pmos(drain,source,gate);
FSYM
SYM #nmos
BB(85,55,105,75)
TITLE 100 70 #nmos
MODEL 901
PROP 2.4 1.2
REC(170,-40,0,0)
VIS 1
PIN(85,75,0.000,0)source
PIN(95,55,0.000,0)gate
PIN(105,75,7.000,30)drain
LIG(95,65,95,55)
LIG(101,65,89,65)
LIG(101,67,89,67)
LIG(89,75,89,67)
LIG(85,75,89,75)
LIG(101,75,101,67)
LIG(105,75,101,75)
VLG nmos nmos(drain,source,gate);
FSYM
SYM #light
BB(268,85,274,99)
TITLE 270 100 #light
MODEL 49
PROP
REC(269,87,4,5)
VIS 1
PIN(270,100,0.000,0)Output
LIG(273,92,273,87)
LIG(273,87,272,86)
LIG(269,87,269,92)
LIG(272,97,272,94)
LIG(271,97,274,97)
LIG(271,99,273,97)
LIG(272,99,274,97)
LIG(268,94,274,94)
LIG(270,94,270,100)
LIG(268,92,268,94)
LIG(274,92,268,92)
LIG(274,94,274,92)
LIG(270,86,269,87)
LIG(272,86,270,86)
FSYM
SYM #vss
BB(240,142,250,150)
TITLE 244 147 #vss
MODEL 0
PROP
REC(105,45,0,0)
VIS 0
PIN(245,140,0.000,0).
LIG(245,140,245,145)
LIG(240,145,250,145)
LIG(240,148,242,145)
LIG(242,148,244,145)
LIG(244,148,246,145)
LIG(246,148,248,145)
FSYM
SYM #vdd
BB(240,50,250,60)
TITLE 243 56 #vdd
MODEL 1
PROP
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