/* snds100.h - Samsung SNDS100 header file */


/*
modification history
--------------------
01b,08feb99,ak/knp added iic register definitions
01a,20aug99,ak/knp created for snds100
*/

/*
This file contains I/O address and related constants for the ARM SNDS100 board.
*/

#ifndef	INCsndsh
#define	INCsndsh

#define TARGET_SNDS


#ifdef INCLUDE_FLASH
#define FLASH_ADRS	0x4000000 /* Base address of Flash part */
#define FLASH_WIDTH	1	  /* 1 byte-wide part */

#if (CPU == ARM710A)
#define SYS_FLASH_BOARD_DELAY
#define SYS_FLASH_DELAY_SHIFT 0
#define SYS_FLASH_DELAY_ADJ 0
#define SYS_FLASH_DELAY_INCR 1
#elif (CPU == ARM7TDMI_T)
#undef  SYS_FLASH_BOARD_DELAY
#define SYS_FLASH_DELAY_SHIFT 3
#define SYS_FLASH_DELAY_ADJ 0
#define SYS_FLASH_DELAY_INCR 3
#elif (CPU == ARM7TDMI)
#define SYS_FLASH_BOARD_DELAY
#define SYS_FLASH_DELAY_SHIFT 0
#define SYS_FLASH_DELAY_ADJ 0
#define SYS_FLASH_DELAY_INCR 1
#else
#error CPU type not handled by Flash timings in pid7t.h 
#endif /* CPU == ARM710A */
#endif /* INCLUDE_FLASH */


/*
 * Local-to-Bus memory address constants:
 * the local memory address always appears at 0 locally;
 * it is not dual ported.
 */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed */
#define LOCAL_MEM_BUS_ADRS	0x00000000	/* fixed */


#define BUS		BUS_TYPE_NONE


#define SNDS_CPU_SPEED	50000000	/* CPU clocked at 16 MHz. The timer */
					/* speed is related to this */


/*************************************************************************
* changes made from here
*/

/*************************************************************************
* KS32C50100 SPECIAL REGISTERS 
*
*/

#define ASIC_BASE  		0x3ff0000

/* Interrupt Control */

#define INT_CNTRL_BASE 		(ASIC_BASE+0x4000) /*Define base of all interrupt */

/*SYSTEM MANAGER REGISTERS */

#define SNDS_SYSCFG			(ASIC_BASE+0x0000)
#define SNDS_CLKCON  		(ASIC_BASE+0x3000)
#define SNDS_EXTACON0  		(ASIC_BASE+0x3008)
#define SNDS_EXTACON1  		(ASIC_BASE+0x300c)
#define SNDS_EXTDBWTH  		(ASIC_BASE+0x3010)
#define SNDS_ROMCON0  		(ASIC_BASE+0x3014)
#define SNDS_ROMCON1  		(ASIC_BASE+0x3018)
#define SNDS_ROMCON2  		(ASIC_BASE+0x301c)
#define SNDS_ROMCON3  		(ASIC_BASE+0x3020)
#define SNDS_ROMCON4  		(ASIC_BASE+0x3024)
#define SNDS_ROMCON5  		(ASIC_BASE+0x3028)
#define SNDS_DRAMCON0  		(ASIC_BASE+0x302c)
#define SNDS_DRAMCON1  		(ASIC_BASE+0x3030)
#define SNDS_DRAMCON2  		(ASIC_BASE+0x3034)
#define SNDS_DRAMCON3  		(ASIC_BASE+0x3038)
#define SNDS_REFEXTCON 		(ASIC_BASE+0x303c)

/* controller registers */
#define SNDS_INTMODE 		(ASIC_BASE+0x4000)
#define SNDS_INTPEND 		(ASIC_BASE+0x4004)
#define SNDS_INTMASK 		(ASIC_BASE+0x4008)
#define SNDS_INTOFFSET 		(ASIC_BASE+0x4024)
#define SNDS_INTPENDTST 	(ASIC_BASE+0x402c)

#define INT_DISABLE             0x1fffff

#define SNDS_INTPRI0 		(ASIC_BASE+0x400C)
#define SNDS_INTPRI1 		(ASIC_BASE+0x4010)
#define SNDS_INTPRI2 		(ASIC_BASE+0x4014)
#define SNDS_INTPRI3 		(ASIC_BASE+0x4018)
#define SNDS_INTPRI4 		(ASIC_BASE+0x401C)
#define SNDS_INTPRI5 		(ASIC_BASE+0x4020)

#define SNDS_INTOSET_FIQ 	(ASIC_BASE+0x4030)
#define SNDS_INTOSET_IRQ 	(ASIC_BASE+0x4034)

 /* I/O Port Interface  */

#define SNDS_IOPMOD 		(ASIC_BASE+0x5000)
#define SNDS_IOPCON 		(ASIC_BASE+0x5004)
#define SNDS_IOPDATA 		(ASIC_BASE+0x5008)

/* IIC Registers */
#define  SNDS_IICCON   (ASIC_BASE+0xf000)
#define  SNDS_IICBUF    (ASIC_BASE+0xf004)
#define  SNDS_IICPS   (ASIC_BASE+0xf008)
#define  SNDS_IICCNT  (ASIC_BASE+0xf00c)

/* definitions for the KS32C50100 DUART */

#define N_SIO_CHANNELS		N_SNDS_UART_CHANNELS
#define N_UART_CHANNELS		N_SNDS_UART_CHANNELS
#define N_SNDS_UART_CHANNELS	2		/* number of SNDS UART chans */
#define UART_REG_ADDR_INTERVAL	1		/* registers 4 bytes apart */
#define SERIAL_A_BASE_ADR	(ASIC_BASE+0xD000)/* UART A base address */
#define SERIAL_B_BASE_ADR	(ASIC_BASE+0xE000)/* UART B base address */

#define PARALLEL_BASE_ADR	0x0D800040	/* parallel port base ???*/


/*************************************************************************
*
* DRAM Memory Bank 0 area MAP for Exception vector table 
* and Stack, User code area. 
*
*/

#define DRAM_BASE  	0x0	/* Final start address of DRAM */
#define DRAM_LIMIT 	0x400000
#define	RESET_DRAM_START	0x1000000	/* Start of DRAM on power-up */
#define	RESET_ROM_START	0x0	/* Start od ROM on power-up */

/****************************************************************************
*
* Format of the Program Status Register 
*/

#define FBit 	 	0x40
#define IBit  	 	0x80
#define LOCKOUT  	0xC0 	/* Interrupt lockout value */
#define LOCK_MSK 	0xC0 	/* Interrupt lockout mask value */
#define MODE_MASK 	0x1F 	/* Processor Mode Mask */
#define UDF_MODE 	0x1B 	/* Undefine Mode(UDF) */
#define ABT_MODE 	0x17 	/* Abort Mode(ABT) */
#define SUP_MODE 	0x13 	/* Supervisor Mode (SVC) */
#define IRQ_MODE 	0x12 	/* Interrupt Mode (IRQ) */
#define FIQ_MODE 	0x11 	/* Fast Interrupt Mode (FIQ) */
#define USR_MODE 	0x10 	/* User Mode(USR) */

/*************************************************************************
* SYSTEM CLOCK 
*/

#define MHz 		 1000000

#define fMCLK_MHz 	 50000000 	/* 50MHz, KS32C50100*/
#define fMCLK 		 fMCLK_MHz/MHz

/*************************************************************************
* SYSTEM MEMORY CONTROL REGISTER EQU TABLES 
*/

/* SYSCFG Register Value */
#define SYSCONFIG_VAL	0x7ffff90	/* System Configuration Value, EDO RAM */
#define SYSCONFIG_VAL_SDRAM	0x87ffff90	/* System Configuration Value, SDRAM */

/* -> EXTDBWTH : Memory Bus Width register */
#define DSR0  (2<<0) 	/* ROM0, 0 : Disable, 1 : Byte etc.*/
#define DSR1  (2<<2) 	/* ROM1  */
#define DSR2  (3<<4)	/* ROM2  */
#define DSR3  (3<<6) 	/* ROM3  */
#define DSR4  (3<<8) 	/* ROM4  */
#define DSR5  (3<<10) 	/* ROM5  */
#define DSD0  (3<<12) 	/* DRAM0 */
#define DSD1  (3<<14) 	/* DRAM1 */
#define DSD2  (3<<16) 	/* DRAM2 */
#define DSD3  (3<<18) 	/* DRAM3 */
#define DSX0  (3<<20) 	/* EXTIO0*/
#define DSX1  (3<<22) 	/* EXTIO1*/
#define DSX2  (3<<24) 	/* EXTIO2*/
#define DSX3  (3<<26) 	/* EXTIO3*/

#define rEXTDBWTH 	(DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3)

/***********************************************************
*
* -> ROMCON0 : ROM Bank0 Control register 
*/
#define ROMBasePtr0	0
#define ROMBasePtr0_S	(0x100<<10) 	/*=0x1000000*/
#define ROMEndPtr0	((ROM_SIZE>>12)<<20) 	/*=0x80000*/
#define ROMEndPtr0_S (((ROM_SIZE>>12)+0x100)<<20) 	/*=0x1800000*/
#define PMC0 	 0x0 		/* 0x0=Normal ROM, 0x1=4Word Page etc.*/
#define rTpa0 	 (0x0<<2) 	/* 0x0=5Cycle, 0x1=2Cycle etc.*/
#define rTacc0 	 (0x6<<4) 	/* 0x0=Disable, 0x1=2Cycle etc.*/
#define rROMCON0 	 (ROMEndPtr0+ROMBasePtr0+rTacc0+rTpa0+PMC0)
#define rROMCON0_S 	 (ROMEndPtr0_S+ROMBasePtr0_S+rTacc0+rTpa0+PMC0)

/***************************************************************************
* -> ROMCON1 : ROM Bank1 Control register 
*/