/***********************************************************************
 * $Workfile:   os_cpu.h  $
 * $Revision:   1.3  $
 * $Author:   WellsK  $
 * $Date:   Apr 27 2004 11:02:28  $
 *
 * Project: MicroCos-II CPU definitions file
 *
 * Description:
 *     This is the CPU specific definitions file for MicroCos-II ported
 *     for the LH7A400 SOC/CSP.
 *
 * Revision History:
 * $Log:   //smaicnt2/pvcs/VM/sharpmcu/archives/sharpmcu/software/csps/lh7a400/ports/ucosii/os_cpu.h-arc  $
 * 
 *    Rev 1.3   Apr 27 2004 11:02:28   WellsK
 * Added IAR support.
 * 
 *    Rev 1.2   Oct 02 2003 09:17:12   WellsK
 * Added 'newline' to the end of the file to make the newline
 * warning go away.
 * 
 *    Rev 1.1   Sep 26 2003 15:27:30   WellsK
 * Corrected inline assembly versions of critical section entry and
 * exit code for GNU and GHS.
 * 
 *    Rev 1.0   Jun 30 2003 15:18:32   WellsK
 * Initial revision.
 * 
 *
 ***********************************************************************
 * SHARP MICROELECTRONICS OF THE AMERICAS MAKES NO REPRESENTATION
 * OR WARRANTIES WITH RESPECT TO THE PERFORMANCE OF THIS SOFTWARE,
 * AND SPECIFICALLY DISCLAIMS ANY RESPONSIBILITY FOR ANY DAMAGES, 
 * SPECIAL OR CONSEQUENTIAL, CONNECTED WITH THE USE OF THIS SOFTWARE.
 *
 * SHARP MICROELECTRONICS OF THE AMERICAS PROVIDES THIS SOFTWARE SOLELY 
 * FOR THE PURPOSE OF SOFTWARE DEVELOPMENT INCORPORATING THE USE OF A 
 * SHARP MICROCONTROLLER OR SYSTEM-ON-CHIP PRODUCT. USE OF THIS SOURCE
 * FILE IMPLIES ACCEPTANCE OF THESE CONDITIONS.
 *
 * COPYRIGHT (C) 2001 SHARP MICROELECTRONICS OF THE AMERICAS, INC.
 *     CAMAS, WA
 **********************************************************************/

#ifndef LH7A400_OS_CPU_H 
#define LH7A400_OS_CPU_H 

#ifdef __ICCARM__
#include "inarm.h"
#endif

#define OS_CPU_GLOBALS

/***********************************************************************
 * Data Types
 * (Compiler Specific for ARM, GHS, and GNU)
 **********************************************************************/

typedef unsigned char    BOOLEAN; /* Boolean type */
typedef unsigned char    INT8U;	  /* Unsigned 8 bit quantity */
typedef signed char      INT8S;	  /* Signed 8 bit quantity */
typedef unsigned short   INT16U;  /* Unsigned 16 bit quantity */
typedef signed short     INT16S;  /* Signed 16 bit quantity */
typedef unsigned long    INT32U;  /* Unsigned 32 bit quantity */
typedef signed long      INT32S;  /* Signed 32 bit quantity */
typedef signed long      FP32;	  /* Single precision floating point */
typedef signed long long FP64;	  /* Double precision floating point */

/* Each stack entry is 32-bits wide */
typedef INT32U OS_STK;

/* CPU Status register is 32-bits wide */
typedef INT32U OS_CPU_SR;

/***********************************************************************
 * LH7A400 specific functions
 **********************************************************************/

#define OS_STK_GROWTH      1     /* Stack grows down */

/* Task switch function */
void OS_TASK_SW(void);

/* ARM critical section entry and exit lock sections */
#ifdef __GNUC__
#define OS_CRITICAL_METHOD 3
#define OS_ENTER_CRITICAL()           \
{                                     \
    register INT32U tmp;              \
    asm                               \
    (                                 \
        "MRS %0, CPSR" "\n\t"         \
        "ORR %1, %0, #0xC0" "\n\t"    \
        "MSR CPSR_c, %1" "\n\t"       \
        : "=r" (cpu_sr), "=r" (tmp)   \
    );                                \
}
#define OS_EXIT_CRITICAL() asm("MSR CPSR_c, %0" "\n\t" :: "r" (cpu_sr));
#endif

#ifdef __ghs__
#define OS_CRITICAL_METHOD 3
#define OS_ENTER_CRITICAL() cpu_sr = ghs_enter_critical()
asm INT32U ghs_enter_critical(void)
{
    STMFD sp!, {r1}     /* May not be needed */
    MRS r0, CPSR
    ORR r1, r0, #0xC0
    MSR CPSR_c, r1
    LDMFD sp!, {r1}     /* May not be needed */
}

#define OS_EXIT_CRITICAL() ghs_exit_critical(cpu_sr)
asm void ghs_exit_critical(INT32U saved_sr)
{
%reg saved_sr
    MSR CPSR_c, saved_sr
}
#endif

#ifdef __arm
#define OS_CRITICAL_METHOD 3
#define OS_ENTER_CRITICAL()           \
{                                     \
    register INT32U tmp;              \
    __asm                             \
    {                                 \
        MRS cpu_sr ,CPSR;             \
        ORR tmp, cpu_sr, ##0xC0;      \
        MSR CPSR_c, tmp               \
    }                                 \
}
#define OS_EXIT_CRITICAL() __asm{MSR CPSR_c, cpu_sr}
#endif

#ifdef __ICCARM__
#define OS_CRITICAL_METHOD 3
#define OS_ENTER_CRITICAL()           \
{                                     \
    cpu_sr = __get_CPSR();            \
    __set_CPSR(cpu_sr | 0xC0);        \
}
#define OS_EXIT_CRITICAL()            \
{                                     \
    __set_CPSR(cpu_sr);               \
}
#endif

#endif /* LH7A400_OS_CPU_H */