?? main.lst
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C51 COMPILER V6.10 MAIN 04/18/2001 16:49:02 PAGE 1
C51 COMPILER V6.10, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN .\MAIN.OBJ
COMPILER INVOKED BY: C:\KEIL\C51\BIN\C51.EXE .\MAIN.C OPTIMIZE(6,SIZE) BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOL
-S
stmt level source
1 /*------------------------------------------------------------------*-
2
3 Main.c (v1.00)
4
5 ------------------------------------------------------------------
6
7 Test program for shared-clock (interrupt) scheduler for 89C52, etc.
8
9 *** Tick 1 - MASTER CODE ***
10
11 *** Both Master and Slave share the same tick rate (1 ms) ***
12
13 Required linker options (see Chapter 14 for details):
14
15 OVERLAY (main ~ (LED_Flash_Update,TRAFFIC_LIGHTS_Update),
16 SCH_Dispatch_Tasks ! (LED_Flash_Update,TRAFFIC_LIGHTS_Update))
17
18
19 COPYRIGHT
20 ---------
21
22 This code is from the book:
23
24 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
25 [Pearson Education, 2001; ISBN: 0-201-33138-1].
26
27 This code is copyright (c) 2001 by Michael J. Pont.
28
29 See book for copyright details and other information.
30
31 -*------------------------------------------------------------------*/
32
33 #include "Main.h"
1 =1 /*------------------------------------------------------------------*-
2 =1
3 =1 Main.H (v1.00)
4 =1
5 =1 ------------------------------------------------------------------
6 =1
7 =1 'Project Header' (see Chap 9) for project SCI_Ti1m (see Chap 26)
8 =1
9 =1
10 =1 COPYRIGHT
11 =1 ---------
12 =1
13 =1 This code is from the book:
14 =1
15 =1 PATTERNS FOR TIME-TRIGGERED EMBEDDED SYSTEMS by Michael J. Pont
16 =1 [Pearson Education, 2001; ISBN: 0-201-33138-1].
17 =1
18 =1 This code is copyright (c) 2001 by Michael J. Pont.
19 =1
20 =1 See book for copyright details and other information.
21 =1
C51 COMPILER V6.10 MAIN 04/18/2001 16:49:02 PAGE 2
22 =1 -*------------------------------------------------------------------*/
23 =1
24 =1 #ifndef _MAIN_H
25 =1 #define _MAIN_H
26 =1
27 =1 //------------------------------------------------------------------
28 =1 // WILL NEED TO EDIT THIS SECTION FOR EVERY PROJECT
29 =1 //------------------------------------------------------------------
30 =1
31 =1 // Must include the appropriate microcontroller header file here
32 =1 #include <AT89x52.h>
1 =2 /*--------------------------------------------------------------------------
2 =2 AT89X52.H
3 =2
4 =2 Header file for the low voltage Flash Atmel AT89C52 and AT89LV52.
5 =2 Copyright (c) 1995-1996 Keil Software, Inc. All rights reserved.
6 =2 --------------------------------------------------------------------------*/
7 =2
8 =2 #ifndef AT89X52_HEADER_FILE
9 =2 #define AT89X52_HEADER_FILE 1
10 =2
11 =2 /*------------------------------------------------
12 =2 Byte Registers
13 =2 ------------------------------------------------*/
14 =2 sfr P0 = 0x80;
15 =2 sfr SP = 0x81;
16 =2 sfr DPL = 0x82;
17 =2 sfr DPH = 0x83;
18 =2 sfr PCON = 0x87;
19 =2 sfr TCON = 0x88;
20 =2 sfr TMOD = 0x89;
21 =2 sfr TL0 = 0x8A;
22 =2 sfr TL1 = 0x8B;
23 =2 sfr TH0 = 0x8C;
24 =2 sfr TH1 = 0x8D;
25 =2 sfr P1 = 0x90;
26 =2 sfr SCON = 0x98;
27 =2 sfr SBUF = 0x99;
28 =2 sfr P2 = 0xA0;
29 =2 sfr IE = 0xA8;
30 =2 sfr P3 = 0xB0;
31 =2 sfr IP = 0xB8;
32 =2 sfr T2CON = 0xC8;
33 =2 sfr T2MOD = 0xC9;
34 =2 sfr RCAP2L = 0xCA;
35 =2 sfr RCAP2H = 0xCB;
36 =2 sfr TL2 = 0xCC;
37 =2 sfr TH2 = 0xCD;
38 =2 sfr PSW = 0xD0;
39 =2 sfr ACC = 0xE0;
40 =2 sfr B = 0xF0;
41 =2
42 =2 /*------------------------------------------------
43 =2 P0 Bit Registers
44 =2 ------------------------------------------------*/
45 =2 sbit P0_0 = 0x80;
46 =2 sbit P0_1 = 0x81;
47 =2 sbit P0_2 = 0x82;
48 =2 sbit P0_3 = 0x83;
49 =2 sbit P0_4 = 0x84;
50 =2 sbit P0_5 = 0x85;
51 =2 sbit P0_6 = 0x86;
C51 COMPILER V6.10 MAIN 04/18/2001 16:49:02 PAGE 3
52 =2 sbit P0_7 = 0x87;
53 =2
54 =2 /*------------------------------------------------
55 =2 PCON Bit Values
56 =2 ------------------------------------------------*/
57 =2 #define IDL_ 0x01
58 =2
59 =2 #define STOP_ 0x02
60 =2 #define PD_ 0x02 /* Alternate definition */
61 =2
62 =2 #define GF0_ 0x04
63 =2 #define GF1_ 0x08
64 =2 #define SMOD_ 0x80
65 =2
66 =2 /*------------------------------------------------
67 =2 TCON Bit Registers
68 =2 ------------------------------------------------*/
69 =2 sbit IT0 = 0x88;
70 =2 sbit IE0 = 0x89;
71 =2 sbit IT1 = 0x8A;
72 =2 sbit IE1 = 0x8B;
73 =2 sbit TR0 = 0x8C;
74 =2 sbit TF0 = 0x8D;
75 =2 sbit TR1 = 0x8E;
76 =2 sbit TF1 = 0x8F;
77 =2
78 =2 /*------------------------------------------------
79 =2 TMOD Bit Values
80 =2 ------------------------------------------------*/
81 =2 #define T0_M0_ 0x01
82 =2 #define T0_M1_ 0x02
83 =2 #define T0_CT_ 0x04
84 =2 #define T0_GATE_ 0x08
85 =2 #define T1_M0_ 0x10
86 =2 #define T1_M1_ 0x20
87 =2 #define T1_CT_ 0x40
88 =2 #define T1_GATE_ 0x80
89 =2
90 =2 #define T1_MASK_ 0xF0
91 =2 #define T0_MASK_ 0x0F
92 =2
93 =2 /*------------------------------------------------
94 =2 P1 Bit Registers
95 =2 ------------------------------------------------*/
96 =2 sbit P1_0 = 0x90;
97 =2 sbit P1_1 = 0x91;
98 =2 sbit P1_2 = 0x92;
99 =2 sbit P1_3 = 0x93;
100 =2 sbit P1_4 = 0x94;
101 =2 sbit P1_5 = 0x95;
102 =2 sbit P1_6 = 0x96;
103 =2 sbit P1_7 = 0x97;
104 =2
105 =2 sbit T2 = 0x90; /* External input to Timer/Counter 2, clock out */
106 =2 sbit T2EX = 0x91; /* Timer/Counter 2 capture/reload trigger & dir ctl */
107 =2
108 =2 /*------------------------------------------------
109 =2 SCON Bit Registers
110 =2 ------------------------------------------------*/
111 =2 sbit RI = 0x98;
112 =2 sbit TI = 0x99;
113 =2 sbit RB8 = 0x9A;
C51 COMPILER V6.10 MAIN 04/18/2001 16:49:02 PAGE 4
114 =2 sbit TB8 = 0x9B;
115 =2 sbit REN = 0x9C;
116 =2 sbit SM2 = 0x9D;
117 =2 sbit SM1 = 0x9E;
118 =2 sbit SM0 = 0x9F;
119 =2
120 =2 /*------------------------------------------------
121 =2 P2 Bit Registers
122 =2 ------------------------------------------------*/
123 =2 sbit P2_0 = 0xA0;
124 =2 sbit P2_1 = 0xA1;
125 =2 sbit P2_2 = 0xA2;
126 =2 sbit P2_3 = 0xA3;
127 =2 sbit P2_4 = 0xA4;
128 =2 sbit P2_5 = 0xA5;
129 =2 sbit P2_6 = 0xA6;
130 =2 sbit P2_7 = 0xA7;
131 =2
132 =2 /*------------------------------------------------
133 =2 IE Bit Registers
134 =2 ------------------------------------------------*/
135 =2 sbit EX0 = 0xA8; /* 1=Enable External interrupt 0 */
136 =2 sbit ET0 = 0xA9; /* 1=Enable Timer 0 interrupt */
137 =2 sbit EX1 = 0xAA; /* 1=Enable External interrupt 1 */
138 =2 sbit ET1 = 0xAB; /* 1=Enable Timer 1 interrupt */
139 =2 sbit ES = 0xAC; /* 1=Enable Serial port interrupt */
140 =2 sbit ET2 = 0xAD; /* 1=Enable Timer 2 interrupt */
141 =2
142 =2 sbit EA = 0xAF; /* 0=Disable all interrupts */
143 =2
144 =2 /*------------------------------------------------
145 =2 P3 Bit Registers (Mnemonics & Ports)
146 =2 ------------------------------------------------*/
147 =2 sbit P3_0 = 0xB0;
148 =2 sbit P3_1 = 0xB1;
149 =2 sbit P3_2 = 0xB2;
150 =2 sbit P3_3 = 0xB3;
151 =2 sbit P3_4 = 0xB4;
152 =2 sbit P3_5 = 0xB5;
153 =2 sbit P3_6 = 0xB6;
154 =2 sbit P3_7 = 0xB7;
155 =2
156 =2 sbit RXD = 0xB0; /* Serial data input */
157 =2 sbit TXD = 0xB1; /* Serial data output */
158 =2 sbit INT0 = 0xB2; /* External interrupt 0 */
159 =2 sbit INT1 = 0xB3; /* External interrupt 1 */
160 =2 sbit T0 = 0xB4; /* Timer 0 external input */
161 =2 sbit T1 = 0xB5; /* Timer 1 external input */
162 =2 sbit WR = 0xB6; /* External data memory write strobe */
163 =2 sbit RD = 0xB7; /* External data memory read strobe */
164 =2
165 =2 /*------------------------------------------------
166 =2 IP Bit Registers
167 =2 ------------------------------------------------*/
168 =2 sbit PX0 = 0xB8;
169 =2 sbit PT0 = 0xB9;
170 =2 sbit PX1 = 0xBA;
171 =2 sbit PT1 = 0xBB;
172 =2 sbit PS = 0xBC;
173 =2 sbit PT2 = 0xBD;
174 =2
175 =2 /*------------------------------------------------
C51 COMPILER V6.10 MAIN 04/18/2001 16:49:02 PAGE 5
176 =2 T2CON Bit Registers
177 =2 ------------------------------------------------*/
178 =2 sbit CP_RL2= 0xC8; /* 0=Reload, 1=Capture select */
179 =2 sbit C_T2 = 0xC9; /* 0=Timer, 1=Counter */
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