;******************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2003 SJTU DSP Tech. Center. All Rights Reserved.
;
;  Description:
;  		TMS320C54x Program for Students Experiment
;
;  History:
;		Date		Authors			Changes
;		2003/29/07	Fu Xuan			Created.
;		2004/07/07	Xu Sheng		Simplified
;******************************************************************************
STACK_ADDR	.set	0x0500

var_x		.set	0
var_y		.set	var_x+1
var_z		.set	var_y+1

off_p		.set	3
off_m		.set	-3
	
	.bss	Data_0,	8		;make sure the data buffer allocated match alignment
	.bss	Data_1,	8		;see cmd file
	
;--------------------------------------------------------------------
	.mmregs
	.global	main
	
	.text
main:
	stm		STACK_ADDR, SP
	stm		#0x00a8, PMST	;IPTR=0x0080
	stm		#0x0000, SWWSR	;reset software wait-state register
	
	sub		A 				;A=0
	stm		#Data_0, AR2	;AR2->Data_0[0]
	stm		#8-1, BRC		;repeat 8 times
	rptb	initial_loop-1
	add		#1, A			;Data_0[8]={1, 2, 3, 4, 5, 6, 7, 8}
	stl		A, *AR2+
initial_loop:

;--------------------------------------------------------------------
;Immediate Addressing
	ld		#0x0100, A		;A=0x0100
	add		#0x0100, 2, A	;A=0x0500
	
;--------------------------------------------------------------------
;Absolute Addressing
	stl		A, *(Data_0)	;Data_0[0]=0x0500

	stm		#0x1234, AR2	;AR2=0x1234
	stm		#Data_1, AR3	;AR3->Data_1[0]
	mvkd	AR2, *AR3		;Data_1[0]=0x1234

	ld		*(Data_1), B	;B=0x1234
	
;--------------------------------------------------------------------
;Accummulator Addressing

	ld		#0x1000, A		;A=0x1234
	stm		#Data_1, AR2	;AR2->Data_1[0]
	rpt		#8-1
	reada	*AR2+			;Data_1[i] would be the same as an array
							;with 8 data, which start at 0x1000
							;Data_1[8]={0x7718, 0x0500, 0x771D, 0x00A8,
							;			0x7728, 0x0000, 0xF020, 0x0100}
	sub		B				;B=0
	ld		#acc_branch, A	;A=acc_branch
	bacc	A				;jump to acc_branch
	add		#1, B			;this is skipped, not executed
	
acc_branch:
	ld		B, A			;A=B=0
	
;--------------------------------------------------------------------
;Direct Addressing
	;test DP direct addressing
	rsbx	CPL 			;CPL=0, DP[8:0] to be high 9 bits of actual address,
							;low 7 bits from instruction
	ld		#Data_0, DP		;load high 9 bits of Data_0 to DP
	nop						;pipeline consideration
	nop						;(see 《數(shù)字信號(hào)處理系統(tǒng)的應(yīng)用和設(shè)計(jì)》P117 Table 4-32)
	ld		@Data_0, A
	add		@Data_1, A		;A=Data_0[0]+Data_1[0]
	stl		A, @Data_1		;store result to Data_1[0]

	;test SP direct addressing
	frame	#off_m			;SP = (SP) - 3 = 0x04FD,  make 3 empty word for use
	ssbx	CPL				;CPL=1, actual address=SP+low 7 bits from instruction
							;pipeline consideration
	sub		B				;B=0
	stm		#Data_0, AR2	;AR2->Data_0[0]
	ld		*AR2+, A		
	add		A, B			;B=sum(Data_0[i])
	stl		B, @(var_x)		;store B to *(SP+0)
	stl		A, @(var_y)		;store Data_0[i] to *(SP+1)

	ld		@(var_x), A		;A=sum(Data_0[i])=0x0024
	add		@(var_y), A		;A=sum(Data_0[i])+Data_0[7]
	stl		A, @(var_z)		;save result to *(SP+2), A=0x002C

	ld		@(var_z), B		;B=A
	sub		A, B			;B=0

	frame	#off_p			;SP = (SP) + 3 = 0x0500, back SP to free 3 words
		
;--------------------------------------------------------------------
;Indirect Addressing
	stm		#Data_0, AR2	;AR2->Data_0[0]
	stm		#Data_1, AR3	;AR3->Data_1[0]
	rpt		#8-1			
	mvdd	*AR2+, *AR3+	;Data_1[i]=Data_0[i], i=0, 1, 2 ... 7
							;Data_0, Data_1: 1 2 3 4 5 6 7 8
	
	sub		A				;A=0
	stm		#5, BK			;circular buffer length is 5
	stm		#Data_0, AR2	;AR2=&Data_0[0]
	stm		#Data_1, AR3	;AR3=&Data_1[0]
	stm		#3, AR0	
	add		*AR2+0%, *AR3+, B
	add		*AR2+0%, *AR3+, B
	add		*AR2+0%, *AR3+, B

	stm		#Data_1, AR3	;AR3=&Data_1[0]
	mvmm	AR3, AR2		;AR2=&Data_1[0]
	mar		*+AR3(3)		;AR3=&Data_1[3]
	ld		*AR3, A			;A=Data_1[3]=4
	ld		*+AR2(3), B		;B=Data_1[3]=4, AR2=&Data_1[3]
	
;--------------------------------------------------------------------
;Memory-Mapped Register Addressing
	;high 9 bits be 0s, direct addressing
	stm		#Data_0, AR6	;AR6=&Data_0[0]=0x2000
	mvmm	AR6, AR7		;AR7=AR6=0x2000
	ldm		AR6, A			;A=AR6=0x2000
	stlm	A,AR2			;AR2=AR6=0x2000
	
;--------------------------------------------------------------------
;Stack Addressing
	call	stack_addressing
	
;--------------------------------------------------------------------
;example
	call	example
	
dead_loop:
	nop
	nop
	nop
	nop
	b 		dead_loop
	
;********************************************************************************
stack_addressing:
	pshm	AR7				;AR7=0x2000, push it to stack to protect enviroments
		
	stm		#Data_0, AR2
	stm		#Data_1+7, AR3
	stm		#8-1, AR7		;repeat 8 times
transfer:	
	pshd	*AR2			;push data to stack
							;view memory from 0x04F6 to 0x04FD, the content is 
							;8 7 6 5 4 3 2 1 (to understand the SP modification)
	mvdd	*AR3-, *AR2+	;Data_0[i]=Data_1[7-i], Data_0[8]={8, 7, 6, 5, 4, 3, 2, 1}
	banz	transfer, *AR7-	
	
	mar		*AR2-			;AR2=&Data_0[7]
	rpt		#8-1			;pop Data_0[i] from stack, restore values
	popd	*AR2-			;Data_0[8]={1, 2, 3, 4, 5, 6, 7, 8}
	
	popm	AR7				;AR7=0x2000
	ret
	
;********************************************************************************
;Demo for exercise
example:

;	temp=0;
;	for(i=0;i<8;i++)
;	{	temp=temp+i;
;		Data_0[i]=temp;
;	}
	sub		A
	sub		B
	stm		#Data_0, AR2
	stm		#8-1, BRC
	
	rptb	next_init - 1
	add		B, A			;temp=temp+i
	stl		A, *AR2+		;Data_0[i]=temp, Data_0: 0 1 3 6 10 15 21 28
	add		#1, B			;i=0, 1, ... 7
next_init:

;	for(i=0;i<8;i++)
;		Data_1[i]=0;
	stm		#Data_1, AR3
	rptz	A, #8-1			;Data_1[i]=0, i=0, 1, ... 7
	stl		A, *AR3+
	
;	Data_1[3]=Data_0[5];
;	Data_1[5]=Data_0[3];
	stm		#Data_0, AR2
	stm		#Data_1, AR3
	ld		*AR2(5), A
	stl		A, *AR3(3)		;Data_1[3]=Data_0[5]
	ld		*AR2(3), A
	stl		A, *AR3(5)		;Data_1[5]=Data_0[3]
	
;	for(i=0;i<4;i++)
;	{	temp=Data_0[i];
;		Data_0[i]=Data_0[7-i];
;		Data_0[7-i]=temp;
;	}
	mvmm	AR2, AR3
	mar		*+AR3(7)		;AR3=&Data_0[7]
	stm		#4-1, BRC
	rptb	end_of_example - 1
	ld		*AR2, A			;temp=Data_0[i]
	mvdd	*AR3, *AR2+		;Data_0[i]=Data_0[7-i]
	stl		A, *AR3-		;Data_0[7-i]=temp
end_of_example:

	ret
	
;********************************************************************************	
	.sect	"vectors"
	
int_RESET:
	b 		main
	nop
	nop
	
	.space	124*16
	
	.end
;end of addressing.s54