<H3>Notes</H3>  [*] means a disp32 with no base if MOD is 00, [ESP] otherwise. This  provides the following addressing modes:<PRE>      disp32[index]        (MOD=00)      disp8[EBP][index]    (MOD=01)      disp32[EBP][index]   (MOD=10)</PRE></EM><H2>17.2.2  How to Read the Instruction Set Pages</H2>The following is an example of the format used for each 80386 instructiondescription in this chapter:<EM><H3>CMC -- Complement Carry Flag</H3><PRE>Opcode   Instruction         Clocks      DescriptionF5        <A HREF="CMC.htm">CMC</A>                  2            Complement carry flag</PRE></EM>The above table is followed by paragraphs labelled "Operation,""Description," "Flags Affected," "Protected Mode Exceptions," "RealAddress Mode Exceptions," and, optionally, "Notes." The following sectionsexplain the notational conventions and abbreviations used in theseparagraphs of the instruction descriptions.<H3>17.2.2.1  Opcode</H3>The "Opcode" column gives the complete object code produced for each formof the instruction. When possible, the codes are given as hexadecimal bytes,in the same order in which they appear in memory. Definitions of entriesother than hexadecimal bytes are as follows:<DL><DT>/digit: <DD>(digit is between 0 and 7) indicates that the ModR/M byte of theinstruction uses only the r/m (register or memory) operand. The reg fieldcontains the digit that provides an extension to the instruction's opcode.<DT>/r: <DD>indicates that the ModR/M byte of the instruction contains both aregister operand and an r/m operand.<DT>cb, cw, cd, cp: <DD>a 1-byte (cb), 2-byte (cw), 4-byte (cd) or 6-byte (cp)value following the opcode that is used to specify a code offset andpossibly a new value for the code segment register.<DT>ib, iw, id: <DD>a 1-byte (ib), 2-byte (iw), or 4-byte (id) immediate operand tothe instruction that follows the opcode, ModR/M bytes or scale-indexingbytes. The opcode determines if the operand is a signed value. All words anddoublewords are given with the low-order byte first.<DT>+rb, +rw, +rd: <DD>a register code, from 0 through 7, added to the hexadecimalbyte given at the left of the plus sign to form a single opcode byte. Thecodes are<PRE>      rb         rw         rd    AL = 0     AX = 0     EAX = 0    CL = 1     CX = 1     ECX = 1    DL = 2     DX = 2     EDX = 2    BL = 3     BX = 3     EBX = 3    AH = 4     SP = 4     ESP = 4    CH = 5     BP = 5     EBP = 5    DH = 6     SI = 6     ESI = 6    BH = 7     DI = 7     EDI = 7</PRE></DL><H3>17.2.2.2  Instruction</H3>The "Instruction" column gives the syntax of the instruction statement asit would appear in an ASM386 program. The following is a list of the symbolsused to represent operands in the instruction statements:<DL><DT>rel8: <DD>a relative address in the range from 128 bytes before the end of theinstruction to 127 bytes after the end of the instruction.<DT>rel16, rel32: <DD>a relative address within the same code segment as theinstruction assembled. rel16 applies to instructions with an operand-sizeattribute of 16 bits; rel32 applies to instructions with an operand-sizeattribute of 32 bits.<DT>ptr16:16, ptr16:32: <DD>a FAR pointer, typically in a code segment differentfrom that of the instruction. The notation 16:16 indicates that the value ofthe pointer has two parts. The value to the right of the colon is a 16-bitselector or value destined for the code segment register. The value to theleft corresponds to the offset within the destination segment. ptr16:16 isused when the instruction's operand-size attribute is 16 bits; ptr16:32 isused with the 32-bit attribute.<DT>r8: <DD>one of the byte registers AL, CL, DL, BL, AH, CH, DH, or BH.<DT>r16: <DD>one of the word registers AX, CX, DX, BX, SP, BP, SI, or DI.<DT>r32: <DD>one of the doubleword registers EAX, ECX, EDX, EBX, ESP, EBP, ESI, orEDI.<DT>imm8: <DD>an immediate byte value. imm8 is a signed number between -128 and+127 inclusive. For instructions in which imm8 is combined with a word ordoubleword operand, the immediate value is sign-extended to form a word ordoubleword. The upper byte of the word is filled with the topmost bit of theimmediate value.<DT>imm16: <DD>an immediate word value used for instructions whose operand-sizeattribute is 16 bits. This is a number between -32768 and +32767 inclusive.<DT>imm32: <DD>an immediate doubleword value used for instructions whoseoperand-size attribute is 32-bits. It allows the use of a number between+2147483647 and -2147483648.<DT>r/m8: <DD>a one-byte operand that is either the contents of a byte register(AL, BL, CL, DL, AH, BH, CH, DH), or a byte from memory.<DT>r/m16: <DD>a word register or memory operand used for instructions whoseoperand-size attribute is 16 bits. The word registers are: AX, BX, CX, DX,SP, BP, SI, DI. The contents of memory are found at the address provided bythe effective address computation.<DT>r/m32: <DD>a doubleword register or memory operand used for instructions whoseoperand-size attribute is 32-bits. The doubleword registers are: EAX, EBX,ECX, EDX, ESP, EBP, ESI, EDI. The contents of memory are found at theaddress provided by the effective address computation.<DT>m8: <DD>a memory byte addressed by DS:SI or ES:DI (used only by stringinstructions).<DT>m16: <DD>a memory word addressed by DS:SI or ES:DI (used only by stringinstructions).<DT>m32: <DD>a memory doubleword addressed by DS:SI or ES:DI (used only by stringinstructions).<DT>m16:16, M16:32: <DD>a memory operand containing a far pointer composed of twonumbers. The number to the left of the colon corresponds to the pointer'ssegment selector. The number to the right corresponds to its offset.<DT>m16 & 32, m16 & 16, m32 & 32: <DD>a memory operand consisting of data item pairswhose sizes are indicated on the left and the right side of the ampersand.All memory addressing modes are allowed. m16 & 16 and m32 & 32 operands areused by the <A HREF="BOUND.htm">BOUND</A> instruction to provide an operand containing an upper andlower bounds for array indices. m16 & 32 is used by <A HREF="LGDT.htm">LIDT</A> and <A HREF="LGDT.htm">LGDT</A> toprovide a word with which to load the limit field, and a doubleword withwhich to load the base field of the corresponding Global and InterruptDescriptor Table Registers.<DT>moffs8, moffs16, moffs32: <DD>(memory offset) a simple memory variable of typeBYTE, WORD, or DWORD used by some variants of the <A HREF="MOV.htm">MOV</A> instruction. Theactual address is given by a simple offset relative to the segment base. NoModR/M byte is used in the instruction. The number shown with moffsindicates its size, which is determined by the address-size attribute of theinstruction.<DT>Sreg: <DD>a segment register. The segment register bit assignments are ES=0,CS=1, SS=2, DS=3, FS=4, and GS=5.</DL><H3>17.2.2.3  Clocks</H3>The "Clocks" column gives the number of clock cycles the instruction takesto execute. The clock count calculations makes the following assumptions:<UL> <LI> The instruction has been prefetched and decoded and is ready for     execution. <LI> Bus cycles do not require wait states. <LI> There are no local bus HOLD requests delaying processor access to the     bus. <LI> No exceptions are detected during instruction execution. <LI> Memory operands are aligned.</UL>Clock counts for instructions that have an r/m (register or memory) operandare separated by a slash. The count to the left is used for a registeroperand; the count to the right is used for a memory operand.<P>The following symbols are used in the clock count specifications:<UL> <LI> n, which represents a number of repetitions. <LI> m, which represents the number of components in the next instruction     executed, where the entire displacement (if any) counts as one     component, the entire immediate data (if any) counts as one component,     and every other byte of the instruction and prefix(es) each counts as     one component. <LI> pm=, a clock count that applies when the instruction executes in     Protected Mode. pm= is not given when the clock counts are the same for     Protected and Real Address Modes.</UL>When an exception occurs during the execution of an instruction and theexception handler is in another task, the instruction execution time isincreased by the number of clocks to effect a task switch. This parameterdepends on several factors:<UL> <LI>The type of TSS used to represent the current task (386 TSS or 286     TSS). <LI>The type of TSS used to represent the new task. <LI>Whether the current task is in V86 mode. <LI>Whether the new task is in V86 mode.</UL>Table 17-5 summarizes the task switch times for exceptions.<PRE>Table 17-5. Task Switch Times for Exceptions                       New TaskOld              386 TSS     286 TSSTask             VM = 0386   VM = 0       309        282TSS386   VM = 1       314        231TSS286                307        282TSS</PRE><H3>17.2.2.4  Description</H3>The "Description" column following the "Clocks" column briefly explains thevarious forms of the instruction. The "Operation" and "Description" sectionscontain more details of the instruction's operation.