<H3>17.2.2.5  Operation</H3>The "Operation" section contains an algorithmic description of theinstruction which uses a notation similar to the Algol or Pascal language.The algorithms are composed of the following elements:<UL><LI> Comments are enclosed within the symbol pairs "(*" and "*)".<LI> Compound statements are enclosed between the keywords of the "if" statement(IF, THEN, ELSE, FI) or of the "do" statement (DO, OD), or of the "case"statement (CASE ... OF, ESAC).<LI> A register name implies the contents of the register. A register nameenclosed in brackets implies the contents of the location whose address iscontained in that register. For example, ES:[DI] indicates the contents ofthe location whose ES segment relative address is in register DI. [SI]indicates the contents of the address contained in register SI relative toSI's default segment (DS) or overridden segment.<LI> Brackets also used for memory operands, where they mean that the contentsof the memory location is a segment-relative offset. For example, [SRC]indicates that the contents of the source operand is a segment-relativeoffset.<LI> A := B; indicates that the value of B is assigned to A.<LI> The symbols =, <>, >=, and <= are relational operators used to compare twovalues, meaning equal, not equal, greater or equal, less or equal,respectively. A relational expression such as A = B is TRUE if the value ofA is equal to B; otherwise it is FALSE.</UL>The following identifiers are used in the algorithmic descriptions:<UL> <LI>  OperandSize represents the operand-size attribute of the instruction,     which is either 16 or 32 bits. AddressSize represents the address-size     attribute, which is either 16 or 32 bits. For example,<PRE>   IF instruction = CMPSW   THEN OperandSize  16;   ELSE      IF instruction = CMPSD      THEN OperandSize  32;      FI;   FI;</PRE>indicates that the operand-size attribute depends on the form of the CMPSinstruction used. Refer to the explanation of address-size and operand-sizeattributes at the beginning of this chapter for general guidelines on howthese attributes are determined. <LI> StackAddrSize represents the stack address-size attribute associated     with the instruction, which has a value of 16 or 32 bits, as explained     earlier in the chapter. <LI> SRC represents the source operand. When there are two operands, SRC is     the one on the right. <LI> DEST represents the destination operand. When there are two operands,     DEST is the one on the left. <LI> LeftSRC, RightSRC distinguishes between two operands when both are     source operands. <LI> eSP represents either the SP register or the ESP register depending on     the setting of the B-bit for the current stack segment.</UL>The following functions are used in the algorithmic descriptions:<UL> <LI> Truncate to 16 bits(value) reduces the size of the value to fit in 16     bits by discarding the uppermost bits as needed. <LI> Addr(operand) returns the effective address of the operand (the result     of the effective address calculation prior to adding the segment base). <LI> ZeroExtend(value) returns a value zero-extended to the operand-size     attribute of the instruction. For example, if OperandSize = 32,     ZeroExtend of a byte value of -10 converts the byte from F6H to     doubleword with hexadecimal value 000000F6H. If the value passed to     ZeroExtend and the operand-size attribute are the same size,     ZeroExtend returns the value unaltered. <LI> SignExtend(value) returns a value sign-extended to the operand-size     attribute of the instruction. For example, if OperandSize = 32,     SignExtend of a byte containing the value -10 converts the byte from     F6H to a doubleword with hexadecimal value FFFFFFF6H. If the value     passed to SignExtend and the operand-size attribute are the same size,     SignExtend returns the value unaltered. <LI> Push(value) pushes a value onto the stack. The number of bytes pushed     is determined by the operand-size attribute of the instruction. The     action of Push is as follows:<PRE>   IF StackAddrSize = 16   THEN      IF OperandSize = 16      THEN         SP  SP - 2;         SS:[SP]  value; (* 2 bytes assigned starting at                             byte address in SP *)      ELSE (* OperandSize = 32 *)         SP  SP - 4;         SS:[SP]  value; (* 4 bytes assigned starting at                             byte address in SP *)      FI;   ELSE (* StackAddrSize = 32 *)      IF OperandSize = 16      THEN         ESP  ESP - 2;         SS:[ESP]  value; (* 2 bytes assigned starting at                              byte address in ESP*)      ELSE (* OperandSize = 32 *)         ESP  ESP - 4;         SS:[ESP]  value; (* 4 bytes assigned starting at                              byte address in ESP*)      FI;   FI;</PRE> <LI> Pop(value) removes the value from the top of the stack and returns it.     The statement EAX  Pop( ); assigns to EAX the 32-bit value that Pop     took from the top of the stack. Pop will return either a word or a     doubleword depending on the operand-size attribute. The action of Pop     is as follows:<PRE>   IF StackAddrSize = 16   THEN      IF OperandSize = 16      THEN         ret val  SS:[SP]; (* 2-byte value *)         SP  SP + 2;      ELSE (* OperandSize = 32 *)         ret val  SS:[SP]; (* 4-byte value *)         SP  SP + 4;      FI;   ELSE (* StackAddrSize = 32 *)      IF OperandSize = 16      THEN         ret val  SS:[ESP]; (* 2 bytes value *)         ESP  ESP + 2;      ELSE (* OperandSize = 32 *)         ret val  SS:[ESP]; (* 4 bytes value *)         ESP  ESP + 4;      FI;   FI;   RETURN(ret val); (*returns a word or doubleword*)</PRE> <LI> Bit[BitBase, BitOffset] returns the address of a bit within a bit     string, which is a sequence of bits in memory or a register. Bits are     numbered from low-order to high-order within registers and within     memory bytes. In memory, the two bytes of a word are stored with the     low-order byte at the lower address.<P>   If the base operand is a register, the offset can be in the range 0..31.   This offset addresses a bit within the indicated register. An example,   "BIT[EAX, 21]," is illustrated in <A HREF="#fig17-3">Figure 17-3</A>  .<P>   If BitBase is a memory address, BitOffset can range from -2 gigabits to 2   gigabits. The addressed bit is numbered (Offset MOD 8) within the byte at   address (BitBase + (BitOffset DIV 8)), where DIV is signed division with   rounding towards negative infinity, and MOD returns a positive number.   This is illustrated in <A HREF="#fig17-4">Figure 17-4</A>  . <LI> I-O-Permission(I-O-Address, width) returns TRUE or FALSE depending on   the I/O permission bitmap and other factors. This function is defined as   follows:<PRE>   IF TSS type is 286 THEN RETURN FALSE; FI;   Ptr  [TSS + 66]; (* fetch bitmap pointer *)   BitStringAddr  SHR (I-O-Address, 3) + Ptr;   MaskShift  I-O-Address AND 7;   CASE width OF:         BYTE: nBitMask  1;         WORD: nBitMask  3;         DWORD: nBitMask  15;   ESAC;   mask  SHL (nBitMask, MaskShift);   CheckString  [BitStringAddr] AND mask;   IF CheckString = 0   THEN RETURN (TRUE);   ELSE RETURN (FALSE);   FI;</PRE> <LI> Switch-Tasks is the task switching function described in  <A HREF="c07.htm">Chapter 7</A>.<H3>17.2.2.6  Description</H3>The "Description" section contains further explanation of the instruction'soperation.<P><A NAME="fig17-3"><IMG align=center SRC="fig17-3.gif" border=0><P><A NAME="fig17-4"><IMG align=center SRC="fig17-4.gif" border=0><H3>17.2.2.7  Flags Affected</H3>The "Flags Affected" section lists the flags that are affected by theinstruction, as follows:<UL> <LI> If a flag is always cleared or always set by the instruction, the     value is given (0 or 1) after the flag name. Arithmetic and logical     instructions usually assign values to the status flags in the uniform     manner described in <A HREF="appc.htm">Appendix C</A>. Nonconventional assignments are     described in the "Operation" section. <LI> The values of flags listed as "undefined" may be changed by the     instruction in an indeterminate manner.</UL>All flags not listed are unchanged by the instruction.<H3>17.2.2.8  Protected Mode Exceptions</H3>This section lists the exceptions that can occur when the instruction isexecuted in 80386 Protected Mode. The exception names are a pound sign (#)followed by two letters and an optional error code in parentheses. Forexample, #GP(0) denotes a general protection exception with an error code of0. Table 17-6 associates each two-letter name with the correspondinginterrupt number.<P><A HREF="c09.htm">Chapter 9</A>   describes the exceptions and the 80386 state upon entry to theexception.<P>Application programmers should consult the documentation provided withtheir operating systems to determine the actions taken when exceptionsoccur.<PRE>Table 17-6. 80386 ExceptionsMnemonic     Interrupt    Description#UD           6           Invalid opcode#NM           7           Coprocessor not available#DF           8           Double fault#TS          10           Invalid TSS#NP          11           Segment or gate not present#SS          12           Stack fault#GP          13           General protection fault#PF          14           Page fault#MF          16           Math (coprocessor) fault</PRE><H3>17.2.2.9  Real Address Mode Exceptions</H3>Because less error checking is performed by the 80386 in Real Address Mode,this mode has fewer exception conditions . Refer to <A HREF="c14.htm">Chapter 14</A>   for furtherinformation on these exceptions.<H3>17.2.2.10  Virtual-8086 Mode Exceptions</H3>Virtual 8086 tasks provide the ability to simulate Virtual 8086 machines.Virtual 8086 Mode exceptions are similar to those for the 8086 processor,but there are some differences . Refer to <A HREF="c15.htm">Chapter 15</A>   for details .<P><HR><P><B>up:</B> <A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A><BR><B>prev:</B> <A HREF="s17_01.htm">17.1 Operand Size and Address-Size Attributes</A><BR><B>next:</B> <A HREF="AAA.htm"> AAA ASCII Adjust after Addition</A></BODY>