#ifndef INC_MX1#define INC_MX1#include "type.h"// PORT A registers#define PORTA_BASE      0xF021C000#define _reg_PTA_GIUS   (*((volatile U32 *)(PORTA_BASE+0x20)))#define _reg_PTA_OCR1   (*((volatile U32 *)(PORTA_BASE+0x04)))#define _reg_PTA_PUEN   (*((volatile U32 *)(PORTA_BASE+0x40)))#define _reg_PTA_DDIR   (*((volatile U32 *)(PORTA_BASE+0x00)))#define _reg_PTA_DR     (*((volatile U32 *)(PORTA_BASE+0x1C)))#define _reg_PTA_GPR    (*((volatile U32 *)(PORTA_BASE+0x38)))// PORT B registers#define PORTB_BASE      0xF021C100#define _reg_PTB_GIUS   (*((volatile U32 *)(PORTB_BASE+0x20)))#define _reg_PTB_OCR1   (*((volatile U32 *)(PORTB_BASE+0x04)))#define _reg_PTB_PUEN   (*((volatile U32 *)(PORTB_BASE+0x40)))#define _reg_PTB_DDIR   (*((volatile U32 *)(PORTB_BASE+0x00)))#define _reg_PTB_DR     (*((volatile U32 *)(PORTB_BASE+0x1C)))#define _reg_PTB_GPR    (*((volatile U32 *)(PORTB_BASE+0x38)))// PORT C registers#define PORTC_BASE      0xF021C200#define _reg_PTC_GIUS   (*((volatile U32 *)(PORTC_BASE+0x20)))#define _reg_PTC_DDIR   (*((volatile U32 *)(PORTC_BASE+0x00)))#define _reg_PTC_SSR    (*((volatile U32 *)(PORTC_BASE+0x24)))#define _reg_PTC_ICR1   (*((volatile U32 *)(PORTC_BASE+0x28)))#define _reg_PTC_ICR2   (*((volatile U32 *)(PORTC_BASE+0x2C)))#define _reg_PTC_IMR    (*((volatile U32 *)(PORTC_BASE+0x30)))#define _reg_PTC_ISR    (*((volatile U32 *)(PORTC_BASE+0x34)))// CS4 registers#define _reg_CS4_CTRLH  (*((volatile U32 *)0xF0220020))#define _reg_CS4_CTRLL  (*((volatile U32 *)0xF0220024))// AITC registers#define AITC_BASE               0xF0223000#define _reg_AITC_NIMASK        (*((volatile U32 *)(AITC_BASE+0x04)))#define _reg_AITC_INTENNUM      (*((volatile U32 *)(AITC_BASE+0x08)))#define _reg_AITC_INTDISNUM     (*((volatile U32 *)(AITC_BASE+0x0C)))#define _reg_AITC_INTTYPEH      (*((volatile U32 *)(AITC_BASE+0x18)))#define _reg_AITC_INTTYPEL      (*((volatile U32 *)(AITC_BASE+0x1C)))#define _reg_AITC_NIPRIORITY1   (*((volatile U32 *)(AITC_BASE+0x38)))#define _reg_AITC_NIVECSR       (*((volatile U32 *)(AITC_BASE+0x40)))// Timer 1 registers#define TIMER1_BASE             0xF0202000#define _reg_TMR_TCTL1          (*((volatile U32 *)(TIMER1_BASE+0x00)))#define _reg_TMR_TPRER1         (*((volatile U32 *)(TIMER1_BASE+0x04)))#define _reg_TMR_TCMP1          (*((volatile U32 *)(TIMER1_BASE+0x08)))#define _reg_TMR_TSTAT1         (*((volatile U32 *)(TIMER1_BASE+0x14)))// Real Time Clock registers#define RTC_BASE                0xF0204000#define _reg_RTC_RCCTL          (*((volatile U32 *)(RTC_BASE+0x10)))#define _reg_RTC_RTCISR         (*((volatile U32 *)(RTC_BASE+0x14)))#define _reg_RTC_RTCIENR        (*((volatile U32 *)(RTC_BASE+0x18)))#define FRR         0x0100  // Free Running/Restart (bit 8)#define IRQEN       0x0010  // IRQ enable (bit 4)#define CLKSOURCE   0x000E  // clock source (bit 3-1)#define TEN         0x0001  // timer enable (bit 0)// Clock control module registers#define CCM_BASE						0xF021B000#define _reg_CCM_CSCR				(*((volatile U32 *)(CCM_BASE+0x00)))#define _reg_CCM_MPCTL0				(*((volatile U32 *)(CCM_BASE+0x04)))// USBD registers#define USBD_BASE						0xF0212000#define _reg_USBD_STAT				(*((volatile U32 *)(USBD_BASE+0x008)))#define _reg_USBD_CTRL				(*((volatile U32 *)(USBD_BASE+0x00C)))#define _reg_USBD_CFGBSY			(*((volatile U32 *)(USBD_BASE+0x010)))#define _reg_USBD_EPBUF				(*((volatile U32 *)(USBD_BASE+0x014)))#define _reg_USBD_INTR_STAT		(*((volatile U32 *)(USBD_BASE+0x018)))#define _reg_USBD_INTR_MASK		(*((volatile U32 *)(USBD_BASE+0x01C)))#define _reg_USBD_ENABLE			(*((volatile U32 *)(USBD_BASE+0x024)))#define _reg_USBD_EP0_STAT			(*((volatile U32 *)(USBD_BASE+0x030)))#define _reg_USBD_EP0_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x034)))#define _reg_USBD_EP0_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x038)))#define _reg_USBD_EP0_FDAT			(*((volatile U32 *)(USBD_BASE+0x03C)))#define _reg_USBD_EP0_FCTRL		(*((volatile U32 *)(USBD_BASE+0x044)))#define _reg_USBD_EP0_FALRM		(*((volatile U32 *)(USBD_BASE+0x050)))#define _reg_USBD_EP1_STAT			(*((volatile U32 *)(USBD_BASE+0x060)))#define _reg_USBD_EP1_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x064)))#define _reg_USBD_EP1_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x068)))#define _reg_USBD_EP1_FDAT			(*((volatile U32 *)(USBD_BASE+0x06C)))#define _reg_USBD_EP1_FCTRL		(*((volatile U32 *)(USBD_BASE+0x074)))#define _reg_USBD_EP1_FALRM		(*((volatile U32 *)(USBD_BASE+0x080)))#define _reg_USBD_EP2_STAT			(*((volatile U32 *)(USBD_BASE+0x090)))#define _reg_USBD_EP2_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x094)))#define _reg_USBD_EP2_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x098)))#define _reg_USBD_EP2_FDAT			(*((volatile U32 *)(USBD_BASE+0x09C)))#define _reg_USBD_EP2_FCTRL		(*((volatile U32 *)(USBD_BASE+0x0A4)))#define _reg_USBD_EP2_FALRM		(*((volatile U32 *)(USBD_BASE+0x0B0)))#define _reg_USBD_EP3_STAT			(*((volatile U32 *)(USBD_BASE+0x0C0)))#define _reg_USBD_EP3_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x0C4)))#define _reg_USBD_EP3_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x0C8)))#define _reg_USBD_EP3_FDAT			(*((volatile U32 *)(USBD_BASE+0x0CC)))#define _reg_USBD_EP3_FCTRL		(*((volatile U32 *)(USBD_BASE+0x0D4)))#define _reg_USBD_EP3_FALRM		(*((volatile U32 *)(USBD_BASE+0x0E0)))#define _reg_USBD_EP4_STAT			(*((volatile U32 *)(USBD_BASE+0x0F0)))#define _reg_USBD_EP4_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x0F4)))#define _reg_USBD_EP4_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x0F8)))#define _reg_USBD_EP4_FDAT			(*((volatile U32 *)(USBD_BASE+0x0FC)))#define _reg_USBD_EP4_FCTRL		(*((volatile U32 *)(USBD_BASE+0x104)))#define _reg_USBD_EP4_FALRM		(*((volatile U32 *)(USBD_BASE+0x110)))#define _reg_USBD_EP5_STAT			(*((volatile U32 *)(USBD_BASE+0x120)))#define _reg_USBD_EP5_INTR_STAT	(*((volatile U32 *)(USBD_BASE+0x124)))#define _reg_USBD_EP5_INTR_MASK	(*((volatile U32 *)(USBD_BASE+0x128)))#define _reg_USBD_EP5_FDAT			(*((volatile U32 *)(USBD_BASE+0x12C)))#define _reg_USBD_EP5_FCTRL		(*((volatile U32 *)(USBD_BASE+0x134)))#define _reg_USBD_EP5_FALRM		(*((volatile U32 *)(USBD_BASE+0x140)))#define MDEVREQ_MASK					0x00000008#define EOT_MASK						0x00000004#define DEVREQ_MASK					0x00000002#define EOF_MASK						0x00000001#define WFR_MASK						0x20000000#define CMD_OVER_MASK				0x00000040#define SOF_MASK						0x00000040#define RST_STOP_MASK				0x00000020#define RST_START_MASK				0x00000010#define CFG_CHG_MASK					0x00000001#define ZLPS_MASK						0x00000004#define FORCE_STALL_MASK			0x00000001// PLAM#define USB_DIV_MASK				0x1C000000// end PLAM#endif