else
      			i=i*4;
    	}
  	return i;
}

BYTE mStar_FineTuneDVIPhase(BYTE channelReg,BYTE channel)
{ BYTE phX, phY, phZ;
  BYTE errX, errY, errZ;

  mStar_WriteByte(TESTEN, channel|ERRD_B); // set test channed
  mStar_WriteByte(TESTEN, channel); // set test channed
  Delay1ms(1);
  mStar_WriteByte(TESTEN, channel|ERRD_B); // set test channed
  errX=mStar_ReadByte(DVI_ERST); // read error status X
  if (errX==0)
    return 0xFF;
  phX=mStar_ReadByte(channelReg);  // read phase X
  phX=GetLinearPhaseValue(phX); // convert to linear Phase;

  mStar_WriteByte(channelReg, DVIPhaseTbl[(phX+8)%0x20]); // write linear phase
  mStar_WriteByte(TESTEN, channel); // set test channed
  Delay1ms(1);
  mStar_WriteByte(TESTEN, channel|ERRD_B); // set test channed
  errY=mStar_ReadByte(DVI_ERST);  // read error status X
  if (errY==0)
    return 0xFF;
  phY=mStar_ReadByte(channelReg);  // read phase X
  phY=GetLinearPhaseValue(phY); // convert to linear Phase;

  mStar_WriteByte(channelReg, DVIPhaseTbl[(phY+8)%0x20]); // write linear phase
  mStar_WriteByte(TESTEN, channel); // set test channed
  Delay1ms(1);
  mStar_WriteByte(TESTEN, channel|ERRD_B); // set test channed
  errZ=mStar_ReadByte(DVI_ERST);  // read error status X
  phZ=mStar_ReadByte(channelReg);  // read phase X
  phZ=GetLinearPhaseValue(phZ); // convert to linear Phase;
  mStar_WriteByte(TESTEN, channel); // set test channed

  if (errX>errY)
    { if (errY>errZ)
        return phZ;
      else
      	return phY;
    }
  else // X<Y
    { if (errX>errZ)
        return phZ;
      else
      	return phX;
    }
}

void mStar_AutoDVI(void)
{ BYTE checkTimes=16;
  BYTE rtValue=0x10;
  BYTE regValue;


  mStar_WriteByte(REGBK, REGBANKADC);
  // auto-setting resistor impendence
  mStar_WriteByte(RT_CTL, rtValue);
  mStar_WriteByte(TESTEN, 0x00); // normal status
  mStar_WriteByte(TESTEN, RDST_B); // freeze/read status
  while (checkTimes--)
    { mStar_WriteByte(TESTEN, 0x00);
      Delay1ms(1);
      mStar_WriteByte(TESTEN, RDST_B); // freeze/read status
      regValue=mStar_ReadByte(RT_STATUS2);
      if (regValue&BIT7)
      	rtValue++;
      else
      	rtValue--;
      rtValue&=0x1F;
      mStar_WriteByte(RT_CTL, rtValue);
    }
  mStar_WriteByte(TESTEN, 0x00); // normal status
  // set best bandwidth
  regValue=mStar_FineTuneBandwidth();
  mStar_WriteByte(TESTEN, TSTEN_B);
  mStar_WriteByte(TESTA0, regValue);
  mStar_WriteByte(TESTEN, 0);
  mStar_WriteByte(REGBK, REGBANKSCALER);

}

Bool mStar_SyncLossStateDetect(void)
{ BYTE fStatus;
  Bool result=FALSE;

  fStatus=mStar_GetInputStatus();
//  Out_i("status %xH", fStatus);//mStar_ReadByte(INSTA));
//  Out_i("stable counter %d", InputTimingStableCounter);
  if (fStatus&SyncLoss)
    {
      if (SrcInputType<Input_Digital)
  	{ mStar_SetAnalogInputPort(); // switch to SOG
          fStatus=mStar_GetInputStatus();
          if (fStatus&SyncLoss)
      	    { mStar_SetAnalogInputPort(); // switch to Separate
              fStatus=mStar_GetInputStatus();
              if (!(fStatus&SyncLoss))
                goto SyncActive;
            }
          else // input timing is coming
            {
            #if 0//ChipID>=ChipAD
              mStar_SetAnalogInputPort(); // switch to Separate
              fStatus=mStar_GetInputStatus(); // check separate sync again
	      if (fStatus&SyncLoss)
	      	{ mStar_SetAnalogInputPort(); // switch to SOG again
                  if (!(fStatus&SyncLoss))
		    goto SyncActive;
	      	}
	      else
	    #endif
                goto SyncActive;
            }
  	}
      if (CableNotConnectedFlag)  // no Cable
        { if (!IsCableNotConnected())
            { Clr_CableNotConnectedFlag();
              result=TRUE;
            }
        }
      else if (IsCableNotConnected()) // no Sync
        { Set_CableNotConnectedFlag();
          result=TRUE;
      	}
      if (PowerSavingFlag)
        { if (SrcInputType==Input_Digital)
            { if (!(mStar_ReadByte(INTCTRL)&0x40) && !(mStar_ReadByte(STATUS2)&0xF0))
                { mStar_PowerUp();
                  Delay1ms(50);
                  fStatus=mStar_GetInputStatus();
                  if (fStatus&SyncLoss)
                    mStar_PowerDown();
                  else
                    result=TRUE;
                }
      	    }
          else if (SrcInputType==Input_YPbPr && mStar_ReadByte(STATUS2)&0x50)
            { if (abs(HFreq(mStar_ReadWord(HSPRD_H))-156)<20)
                { fStatus&=~SyncLoss;
                  result=TRUE;
                }
            }
        }
    }
  else
SyncActive:
    result=TRUE;

  if (result)
    SrcFlags=(SrcFlags&0xF0)|fStatus; // clear others flags, except sync informat (polarity & w/o)

  return result;
}

Bool mStar_ValidTimingDetect(void)
{ BYTE fStatus;

  fStatus=mStar_GetInputStatus();

  if (fStatus&SyncLoss) // no sync
    { SrcFlags=(SrcFlags&0xF0)|fStatus; // clear others flags, except sync informat (polarity & w/o)
      return TRUE;
    }
  else
    { if (SyncPolarity(SrcFlags)!=SyncPolarity(fStatus)) // Sync polarity changed
        { SrcFlags=(SrcFlags&0xF0)|fStatus; // clear others flags, except sync informat (polarity & w/o)
          return TRUE;
  	}
      else
      	{ WORD tempPeriod;

          SrcFlags=(SrcFlags&0xF0)|fStatus; // clear others flags, except sync informat (polarity & w/o)
          tempPeriod=mStar_ReadWord(HSPRD_H)&0x1FFF;
          //Out_i("HPeriod %d", tempPeriod);
          if (InputTimingStableCounter==0)
            SrcHPeriod=tempPeriod;
          if (abs(tempPeriod-SrcHPeriod)>HPeriod_Torlance) // HPeriod changed
            { Out_i("HPeriod %d", tempPeriod);
              return TRUE;
            }

          tempPeriod=mStar_ReadWord(VTOTAL_H)&0x7FF;
          //Out_i("VTotal %d", tempPeriod);
          if (InputTimingStableCounter==0)
            SrcVTotal=tempPeriod;
          if (abs(tempPeriod-SrcVTotal)>VTotal_Torlance) // vtotal changed
            { Out_i("VTotal %d", tempPeriod);
              return TRUE;
            }
      	}
    }
  return FALSE;
}

Bool mStar_FindMode(void)
{ WORD hFreq, vFreq;

#define fStatus	 hFreq
  fStatus=mStar_GetInputStatus();
  if (SyncPolarity(SrcFlags)!=SyncPolarity(fStatus)) // Sync polarity changed
    return FALSE;
  SrcFlags&=0x0F;
#undef fStaus

  hFreq=mStar_ReadWord(HSPRD_H)&0x1FFF;
  Out_i("f HPeriod %d", hFreq);
  if (abs(hFreq-SrcHPeriod)>HPeriod_Torlance) // HPeriod changed
    return FALSE;

  vFreq=mStar_ReadWord(VTOTAL_H)&0x7FF;
  Out_i("f VTotal %d", vFreq);
  if (abs(vFreq-SrcVTotal)>VTotal_Torlance) // vtotal changed
    return FALSE;

  /////////////////////////////////////////////////////////
  SrcHPeriod=hFreq;
  SrcVTotal=vFreq;
  hFreq=HFreq(SrcHPeriod);//((DWORD)MST_CLOCK_MHZ*10+SrcHPeriod/2)/SrcHPeriod; // round 5
  vFreq=VFreq(hFreq, SrcVTotal);//((DWORD)hFreq*1000+(SrcVTotal/2))/SrcVTotal;
//======== for interlace mode
  if (SrcInputType!=Input_Digital && mStar_ReadByte(STATUS2)&INTM_B)
    { SrcFlags|=bInterlaceMode;
      vFreq*=2;
    }
//====================================

  Out_i("HFreq = %d", hFreq);
  Out_i("VFreq = %d", vFreq);
  // check if input timing is out of range
  if (hFreq>MaxInputHFreq || hFreq<MinInputHFreq || vFreq>MaxInputVFreq || vFreq<MinInputVFreq)
    { SrcFlags|=bUnsupportMode;
      return TRUE;
    }

  // search input mode index
  { BYTE modeIndex=0;
    InputModeType *modePtr=StandardMode;
    Bool found=FALSE;

    while (modePtr->HFreq)
      { if (abs(hFreq-modePtr->HFreq)<HFreq_Torlance && abs(vFreq-modePtr->VFreq)<VFreq_Torlance &&
            GetSyncPolarity(SrcFlags)&modePtr->Flags &&
            (SrcFlags&bInterlaceMode)==(modePtr->Flags&bInterlaceMode))
          { found=TRUE;
            SrcModeIndex=modeIndex;
            break;
    	  }
        modePtr++;
        modeIndex++;
      }
    if (!found) // out of standard input range
      { printMsg("cannot find mode in standard mode");
      #define delta	hFreq
      #define minDelta	vFreq
        modeIndex=0;
        modePtr=StandardMode;
        minDelta=VTotal_Delta;
        while (modePtr->HFreq)
          { delta=abs(SrcVTotal-(modePtr->VTotal));
            if (delta<VTotal_Delta && (SrcFlags&bInterlaceMode)==(modePtr->Flags&bInterlaceMode))
              { if (delta<minDelta)
                  { minDelta=delta;
                    SrcModeIndex=modeIndex;
            	  }
                SrcFlags|=bUserMode;
                found=TRUE;
    	      }
            modePtr++;
            modeIndex++;
          }
      #undef delta
      #undef minDelta
      } // out of standard input range
    if (!found)
      SrcFlags|=bUnsupportMode;

   if(   StandardModeGroup==Res_1600x1200
      
      )
          SrcFlags|=bUnsupportMode;


  } // search mode index
  return TRUE;
}

//
BYTE mStar_GetInputStatus(void)
{ BYTE fStatus=0;
  WORD inputValue;
  BYTE status;

  inputValue=mStar_ReadWord(HSPRD_H)&0x1FFF;
  if (inputValue==0x1FFF || inputValue<10)
    fStatus|=bHSyncLoss;

  inputValue=mStar_ReadWord(VTOTAL_H)&0x7FF;
  if (inputValue==0x7FF || inputValue<200)
    fStatus|=bVSyncLoss;

  status=mStar_ReadByte(STATUS2);
  fStatus|=(status&0x03); // Get input timing polarity

  if (SrcInputType==Input_Digital) // input timing is valid while current state is no sync
    { if (mStar_ReadByte(INTCTRL)&0x40)
        { fStatus|=SyncLoss;
        //  printMsg("no digital");
  	}
    }
  else if (!(fStatus&SyncLoss) && SyncLossState()) // input timing is valid while current state is no sync
    { if (SrcInputType<Input_Digital && status&INTM_B)
  	{ mStar_WriteByte(SWRST, GPR_B);
          Delay1ms(1);
          mStar_WriteByte(SWRST, 0);
  	}
      Delay1ms(20);
      if (InputTimingChangeFlag)
        return fStatus;

      status=status&mStar_ReadByte(STATUS2);
      if ((status&3)!=(fStatus&3)) // polarity is stable
      	fStatus|=SyncLoss;
      else if (status&0x30) // SOG or CSync input
        { Delay1ms(20);
          if (InputTimingChangeFlag)
            return fStatus;

          status=mStar_ReadByte(STATUS2);
          // Check if SOG/CSYNC is valid
          if (abs(mStar_ReadWord(VTOTAL_H)-inputValue)>5)
            fStatus|=SyncLoss;
          else if (SrcInputType==Input_YPbPr)
            { if ((status&0x18)!=0x18)
                fStatus|=SyncLoss;
            }
        #if ChipID>=ChipAD
	  else if (status&SOGD_B && mStar_ReadByte(SOGHSPW)>mStar_ReadWord(HSPRD_H)/5)
            fStatus|=SyncLoss;
        #else
          else  if ((status&0x50)==0x50 || (status&0xA0)==0xA0)
      	    fStatus|=SyncLoss;
        #endif
          else if ((status&0x18)==0x18)
            fStatus|=SyncLoss;   // Check if SOG/CSYNC is valid
        }
    }
  return fStatus;
}

Bool IsCableNotConnected(void)
{

#if Quanta || QuantaGateway				// Jason
  return (hwDSUBCable_Pin);// && hwDVICable_Pin);
#else
  return TRUE;
#endif
}