?? ms_reg.h
字號:
typedef enum msbus_direction
{ MS_WRITE,
MS_READ
} msBus_Direction;
// Register Bank Select
#define REGBK 0x00
#define AINC BIT3
#define BUST BIT2
#define REGBANK_MASK 0x3
#define REGBANKSCALER 0x0 //Scaler Bank
#define REGBANKADC 0x1 // ADC Bank
#define REGBANKTCON 0x2 // TCON Bank
#define REGBANK3 0x3 // reverse
// Bank = 01
// Double buffer control
#define DBFC 0x01 // enable dobule buffer while vertical blanking
#define DBC_B BIT0
#define DBL_0 0
#define DBL_1 2
#define DBL_2 4
#define DBL_3 6
//PLL Divider control
#define PLLDIVM 0x02 // PLL divider (HTotal)
#define PLLDIVL 0x03
// input Gain
#define REDGAIN 0x04
#define GRNGAIN 0x05
#define BLUGAIN 0x06
// input Offset
#define REDOFST 0x07
#define GRNOFST 0x08
#define BLUOFST 0x09
// Clamp Timing
#define CLPLACE 0x0A // clamping placement
#define CLDUR 0x0B // clamping duration
// General Control
#define GCTRL 0x0C
#define DRBS BIT0 // DVI R/B swap
#define CSTP BIT1 // Coast polarity 1(d)/0 = H/L
#define WDIS BIT2 // disable pll watchdog timer
#define CCDIS BIT3 // disable clamp during active coast
#define CLPE BIT4 // Clamping edge 0/1= leading/trailing
#define HSLE BIT5 // hsync lock edge 0/1=leading/trailing
#define ECLK BIT6 // internal/external clcok
#define HSP_B BIT7 // Hsync Polarity 1/0 = H/L
// PLL coefficient
#define BWCOEF 0x0D
#define FCOEF 0x0E
#define DCOEF 0x0F
//Clock Phase control
#define CLKCTRL1 0x10
#define CLKCTRL2 0x11
// VCO control
#define VCOCTRL 0x12
// Power management
#define RT_CTL 0x13
// SOG/HSYNC programming levle
#define SOG_LVL 0x14
#define OFIR_B BIT5
#define BMID_B BIT6
#define RMID_B BIT7
#define HS_LVL 0x15
#define RT_STATUS1 0x17
#define RT_STATUS2 0x18
#define PHR_STATUS1 0x19
#define PHR_STATUS2 0x1A
#define DVI_PHR 0x1B
#define DVI_PHG 0x1C
#define DVI_PHB 0x1D
#define DVI_ERST 0x1E
#define DVI_ERTH 0x1F
#define TESTEN 0x20
#define RED_CHANNEL 0x20
#define GREEN_CHANNEL 0x10
#define BLUE_CHANNEL 0x00
#define RDST_B BIT2
#define ERRD_B BIT3
//bit4..5 ERROR status channel select (2: Red, 1:Green, 0:Blue)
#define TSTEN_B BIT7
#define TESTA0 0x21
#define TESTA1 0x22
#define TESTA2 0x23
#define TESTA3 0x24
#define TESTA4 0x25
#define TESTA5 0x26
#define DVIDET_B BIT0 // DVI Clock Detection
#define DMUX_B BIT1 // DVI demultiplexer
#define PHD_B BIT2 // ADCPLL Phase Digitizer
#define DMIBEX_B BIT3 // output current biase
#define DPLBG_B BIT4 // Pll bandgap
#define AMUX_B BIT5 // Analog Mux Override
#define OVRD_B BIT7 // Power Down Overrides
#define TESTA6 0x27
#if 0
#define VREF_B BIT0 // Power down Hsync Voltatge
#define AREF_B BIT2 // power down ADC Voltage reference
#define DPL_B BIT4 // power down PLL
#define ADCB_B BIT5 // Power down ADC Red Channel
#define DDCG_B BIT6 // Power down ADC Red Channel
#define ADCR_B BIT7 // Power down ADC Red Channel
#endif
#define TESTD0 0x28
#define TESTD1 0x29
#define TESTD2 0x2A
#define TESTD3 0x2B
#define TESTD4 0x2C
#define TESTMOD 0x2D
#define TST_REG 0x2E
#define OPAT_B BIT6 // Output picture at test mode
#define EOVB_B BIT7 // Enable override bonding option
//bit0..5 override bonding option
#define PLLCTRLV 0x30
// Bank = 00
// Graphic Port
#define ISELECT 0x02
#define IHSU_B BIT2
#define CSC_B BIT3
#define COMP_B BIT4
#define NIS_B BIT7
#define STYPE_Mask 0x60
#define ISEL_Mask 0xFC
#define ISEL_Analog1 0x00
#define ISEL_Analog2 0x01
#define ISEL_DVI 0x02
#define ISEL_Video 0x03
#define IPCTRL2 0x04
#define HWRP_B BIT0 // input horizontal wrap
#define VWRP_B BIT1 // input vertical wrap
#define ESLS_B BIT2 // early sample line select
#define VSE_B BIT3 // input vsync reference edge
#define HSE_B BIT4 // input hsync reference edge
#define IVSD_B BIT5 // vsync delay select
#define DEON_B BIT6 // DE only
#define DHSR_B BIT7 // Digital input horizontal range
// Input image sample range
#define SPRVST_L 0x05 // V-start
#define SPRVST_H 0x06
#define SPRHST_L 0x07 // H-start
#define SPRHST_H 0x08
#define SPRVDC_L 0x09 // V-
#define SPRVDC_H 0x0A
#define SPRHDC_L 0x0B // H-D
#define SPRHDC_H 0x0C
#define LVL 0x0F // Lock Y line
//Display Timing
#define DEVST_L 0x10 // V-start
#define DEVST_H 0x11
#define DEHST_L 0x12 // h start
#define DEHST_H 0x13
#define DEVEND_L 0x14 // v end
#define DEVEND_H 0x15
#define DEHEND_L 0x16 // h end
#define DEHEND_H 0x17
// scale image window size
#define SIHST_L 0x18
#define SIHST_H 0x19
#define SIVEND_L 0x1A
#define SIVEND_H 0x1B
#define SIHEND_L 0x1C
#define SIHEND_H 0x1D
//output sync timing
#define VDTOT_L 0x1E
#define VDTOT_H 0x1F
#define VSST_L 0x20
#define VSST_H 0x21
#define VSEND_L 0x22
#define VSEND_H 0x23
#define HDTOT_L 0x24
#define HDTOT_H 0x25
#define HSEND 0x26
// output sync control
#define OSCCTRL1 0x27
#define CTRL_B BIT0
#define AHRT_B BIT1
#define MOD2_B BIT2
#define EHTT_B BIT3
#define VSGP_B BIT4
#define HSRM_B BIT5
#define LCM_B BIT6
#define AVOS_B BIT7
#define OSCCTRL2 0x28
#define CRM_B BIT0
#define SLE_B BIT1
#define ATEN2_B BIT5
//brightness control
#define BRC 0x2A
#define BRC_B BIT0 // enable brightness function
#define BCR 0x2B
#define BCG 0x2C
#define BCB 0x2D
// contrast control
#define CNTR 0x2E
#define CNTR_B BIT0 // enable contrast function
#define CNTT_B BIT1 // contrast type select, 0/1 set 0 or 128 as center
#define CCR 0x2F
#define CCG 0x30
#define CCB 0x31
// background color
#define FWC 0x32
#define FWC_B BIT0 // border color on/off
#define FCR 0x33
#define FCG 0x34
#define FCB 0x35
// Dither control
#define DITHCTRL 0x36
#define DITH_B BIT0 // enable dither function
#define OBN_B BIT1 // Output Bit number 0/1:8/6
#define TROT_B BIT2 // temporal coefficient rotate
#define SROT_B BIT3 // Spatial Coefficient Rotate
#define DITHG_BM 0x30
#define DITHG_GM 0xC0
#define DITHCOEF 0x37
#define TRFN 0x38
// gamma control
#define GAMMAC 0x40
#define GCFE_B BIT0 // enable gamma function
#define GTIO_B BIT1 // enable gamme I/O access
#define GammaRed 0
#define GammaGreen 0x4
#define GammaBlue 0x8
#define GammaAll 0xC
#define GAMMAP 0x41
//output control
#define OCTRL1 0x42
#define ERBX_B BIT0
#define ORBX_B BIT1
#define EMLX_B BIT2
#define OMLX_B BIT3
#define LTIM_B BIT4
#define MLXT_B BIT5
#define OCTRL2 0x43
#define DPO_B BIT0 // Dual output
#define DPX_B BIT1 // switch output A, B
#define STO_B BIT2 // stag
#define REV_B BIT3 // revser luminosity
#define BLKS_B BIT4 // black background
#define WHTS_B BIT5 // white
#define DOT_B BIT6 // differential output
#define TCOP_B BIT7 // tcon control
#define OCTRL3 0x44
#define ENRT_B BIT0 // enr TG
#define ENRL_B BIT1 // enr TLRG
#define END_B BIT2 // end TRG
#define ENU_B BIT3 // enu TRG
#define PMOD BIT7 // Power down MOD
#define TTL 0x00 // TTL Output
#define LVDS 0x01 // LVDS Output
#define RSDS_1 0x07 // RSDS Output with vide-side GPO
#define RSDS_2 0x15 // RSDS Output with LVDS-side GPO
#define RSDS 0x1F // RSDS Output with all GPO
//osd alpha blending control
#define BLENDC 0x4B
#define BLENDL 0x4C
// scaling ratio
#define SRH_L 0x50
#define SRH_M 0x51
#define SRH_H 0x52
#define SENH_B BIT7 // Enable Horizontal scaling
#define SRV_L 0x53
#define SRV_M 0x54
#define SRV_H 0x55
#define SENV_B BIT7 // Enable Vertical scaling
// scaling filter control
#define SFH 0x56
#define SFV 0x57
#define HDSUSG 0x58
#define HDSUSL 0x59
#define VDSUSG 0x5A
#define VDSUSL 0x5B
// filter coefficient
#define FTAPEN 0x65
#define FTAPC1 0x66
#define FTAPC2 0x67
#define FTAPC3 0x68
#define FTAPC4 0x69
#define SRGBEN 0x65
#define SRGB12 0x66
#define SRGB13 0x67
#define SRGB21 0x68
#define SRGB23 0x69
#define SRGB31 0x6A
#define SRGB32 0x6B
// interlaced mode line shift
#define INTMDS 0x6F //
#define ODDF_B BIT3 // Shift Odd field
#define ILIM_B BIT4 // insert line
// auto gain function adjust
#define ATGCTRL 0x78
#define ATGR_B BIT1
#define MAXB_B BIT5
#define MAXG_B BIT6
#define MAXR_B BIT7
#define ATGST 0x79
#define MINB_B BIT0
#define MING_B BIT1
#define MINR_B BIT2
//Auto position function and jitter function
#define ATOCTRL 0x7B
#define ATOR_B BIT1
#define AOVDV 0x7C
// auto position function result
#define AOVST_L 0x7E
#define AOVST_H 0x7F
#define AOHST_L 0x80
#define AOHST_H 0x81
#define AOVEND_L 0x82
#define AOVEND_H 0x83
#define AOHEND_L 0x84
#define AOHEND_H 0x85
// jitter detecting result
#define JLST_L 0x86
#define JLST_H 0x87
#define JRST_L 0x88
#define JRST_H 0x89
// Auto phase
#define ATPTH 0x8A
#define ATPCTRL 0x8B
#define ATPR_B BIT1
#define ATPV1 0x8C
#define ATPV2 0x8D
#define ATPV3 0x8E
#define ATPV4 0x8F
// VSync Status
#define ASCTRLL 0x90
#define IVB_B BIT7
#define LSLVP_L 0x91
#define LSLVP_H 0x92
#define LSLW_L 0x93
#define LSLW_H 0x94
#define LVSST_L 0x95
#define LVSST_H 0x96
#define LHTST_L 0x97
#define LHTST_H 0x98
#define LFRST_L 0x99 // locking fraction status
#define LFRST_H 0x9A
#define LHMARGIN 0x9B // Locking htotal margin
#define LRSV_L 0x9C // Locking read start value
#define LRSV_H 0x9D //
#define LSMARGIN 0x9E // Locking SSC margin
////////////////////////// osd control ///////////////////////////////
// OSD i/o access
#define OSDIOA 0xA0
#define ORBW_B BIT1 // Enable OSD register burst write
#define DA_B BIT2 // Enable OSD Display attribute I/O
#define DC_B BIT3 // Enable OSD Display code I/O
#define RF_B BIT4 // Enable OSD RAM font I/O
#define CLR_B BIT6 // OSD clear bit
#define OSBM_B BIT7 // OSD SRAM I/O burst write
// osd address/data port
#define OSDRA 0xA1
#define OSDRD 0xA2
// osd ram font address/data port
#define RAMFA 0xA3
#define RAMFD 0xA4
// osd display code address/data port
#define DISPCA_L 0xA5
#define DISPCA_H 0xA6
#define DISPCD 0xA7
// osd display attribute address/data port
#define DISPAA_L 0xA8
#define DISPAA_H 0xA9
#define DISPAD 0xAA
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