/************************************************************************Source file name : statapi.hDescription:       Interface to ATA/ATAPI driver.COPYRIGHT (C) STMicroelectronics 2000************************************************************************/#ifndef __STATAPI_HAL_H#define __STATAPI_HAL_H/* Includes ---------------------------------------------------------------- */#include "stddefs.h"#include "stcommon.h"#if defined(ATAPI_GPDMA)#include "stgpdma.h"#endif/* For ata_cmd_t definition #include "ata.h"*/#ifdef __cplusplusextern "C" {#endif/* masks to address the control registers - EMI lines */#define         aCS1                0x00040000#define         nCS1                0x00000000#define         aCS0                0x00080000#define         nCS0                0x00000000#define         aDA2                0x00020000#define         nDA2                0x00000000#define         aDA1                0x00010000#define         nDA1                0x00000000#define         aDA0                0x00008000#define         nDA0                0x00000000/*---------------MASKS bits---------------------------*/#define         BIT_0               0x0001#define         BIT_1               0x0002#define         BIT_2               0x0004#define         BIT_3               0x0008#define         BIT_4               0x0010#define         BIT_5               0x0020#define         BIT_6               0x0040#define         BIT_7               0x0080#define         BIT_8               0x0100#define         BIT_9               0x0200#define         BIT_10              0x0400#define         BIT_11              0x0800#define         BIT_12              0x1000#define         BIT_13              0x2000#define         BIT_14              0x4000#define         BIT_15              0x8000#define          DEVHEAD_DEV0       0x00#define          DEVHEAD_DEV1       0x10#define          BSY_BIT_MASK       0x80   /* Busy         */#define          DRQ_BIT_MASK       0x08   /* Data Request */#define          DRDY_BIT_MASK      0x40   /* Device Ready   */#define          DF_BIT_MASK        0x20   /* Device Fault */#define          ERR_BIT_MASK       0x01   /* Error        */#define          nIEN_CLEARED       0x00#define          nIEN_SET           0x02#define          SRST_SET           0x04/* Only used for LBA-48 - High Order Bit, see ATA-6 spec. */#define         CONTROL_HOB         0x128/*---------------HW specific ---------------------------*/#if defined(ST_5514)    #define INT_TIMEOUT     ST_GetClocksPerSecond()#else    #define INT_TIMEOUT     15625*2  /* 2 sec*/#endif/*Exported variables ---------------------------------------------------------*//*Exported macros    ---------------------------------------------------------*/#ifdef ST_5514#define WriteReg(Base, Value)   STSYS_WriteRegDev32LE(Base, Value)#define ReadReg(Base)           STSYS_ReadRegDev32LE(Base)#endif/*Exported constants ---------------------------------------------------------*//* Indexing into array held in hal_atapi.c */typedef enum{       ATA_REG_ALTSTAT = 0,     ATA_REG_DATA ,    ATA_REG_ERROR ,    ATA_REG_FEATURE ,     ATA_REG_SECCOUNT ,    ATA_REG_SECNUM ,     ATA_REG_CYLLOW ,     ATA_REG_CYLHIGH ,    ATA_REG_DEVHEAD ,    ATA_REG_STATUS ,    ATA_REG_COMMAND ,    ATA_REG_CONTROL   } ATA_Register_t;/* ----- 5514-specific details follow in this section ----- */#ifdef ST_5514/* Some relevant HDDI internal registers - see ADCS 7180863 for   name meanings */#define HDDI_MODE               0x080#define HDDI_ATA_RESET          0x084#define HDDI_DMA_ITS            0x0e0#define HDDI_DMA_STA            0x0e4#define HDDI_DMA_ITM            0x0e8/* PIO timing registers */#define HDDI_DPIO_TIMING_OFFSET 0x090#define HDDI_DPIO_I             0x090#define HDDI_DPIO_IORDY         0x094#define HDDI_DPIO_WR            0x098#define HDDI_DPIO_RD            0x09c#define HDDI_DPIO_WREN          0x0a0#define HDDI_DPIO_AH            0x0a4#define HDDI_DPIO_WRRE          0x0a8#define HDDI_DPIO_RDRE          0x0ac/* DMA registers - control, start address, word count, etc. */#define HDDI_DMA_CONTROL_OFFSET 0x0b0#define HDDI_DMA_C              0x0b0#define HDDI_DMA_SA             0x0b4#define HDDI_DMA_WC             0x0b8#define HDDI_DMA_SI             0x0bc#define HDDI_DMA_CA             0x0d0#define HDDI_DMA_CB             0x0d4/* DMA timing - multiword DMA */#define HDDI_MWDMA_TIMING_OFFSET    0x0f0#define HDDI_MWDMA_TD           0x0f0#define HDDI_MWDMA_TH           0x0f4#define HDDI_MWDMA_TJ           0x0f8#define HDDI_MWDMA_TKR          0x0fc#define HDDI_MWDMA_TKW          0x100#define HDDI_MWDMA_TM           0x104#define HDDI_MWDMA_TN           0x108/* DMA timing - UltraDMA */#define HDDI_UDMA_TIMING_OFFSET     0x0f0#define HDDI_UDMA_ACK          0x0f4#define HDDI_UDMA_ENV          0x0f8#define HDDI_UDMA_RP           0x0f0#define HDDI_UDMA_ML           0x104#define HDDI_UDMA_TLI          0x0fc#define HDDI_UDMA_SS           0x100#define HDDI_UDMA_RFS          0x108#define HDDI_UDMA_DVS          0x10c#define HDDI_UDMA_DVH          0x110/* --- DMA configuration registers masks ( hardware specific ) -------- */#define     HDDI_DMA_C_MASK             0x0000001f #define     HDDI_DMA_SA_MASK            0xfffffff0 #define     HDDI_DMA_WC_MASK            0x00ffffff #define     HDDI_DMA_SI_MASK            0x00000003 #define     HDDI_DMA_CA_MASK            0xfffffff0 #define     HDDI_DMA_CB_MASK            0x01ffffff /* Encodes the meanings of bits in the HDDI registers *//* --- HDDI_MODE register (hardware specific) ----------------------- */#define     HDDI_MODE_PIOREG            0x00000000#define     HDDI_MODE_MWDMA             0x00000002#define     HDDI_MODE_UDMA              0x00000003 /* --- HDDI_ATARESET register ------------------- */#define     HDDI_ATARESET_ASSERT        0x00000001#define     HDDI_ATARESET_DEASSERT      0x00000000 /* --- HDDI_ATA_ASR register -------------------- */#define     HDDI_ATA_ASR_ERR            0x00000001#define     HDDI_ATA_ASR_DRQ            0x00000008#define     HDDI_ATA_ASR_DRDY           0x00000040#define     HDDI_ATA_ASR_BSY            0x00000080 /* --- HDDI_ATA_DCR register -------------------- */#define     HDDI_ATA_DCR_nIEN           0x00000002#define     HDDI_ATA_DCR_SRST           0x00000004 /* --- HDDI_ATA_ERR register -------------------- */#define     HDDI_ATA_ERR_ABRT           0x00000004#define     HDDI_ATA_ERR_ICRC           0x00000080 /* DMA CRC error */ /* --- HDDI_ATA_DHR register -------------------- */#define     HDDI_ATA_DHR_DEV0           0x00000000#define     HDDI_ATA_DHR_DEV1           0x00000010#define     HDDI_ATA_DHR_LBA            0x00000040 /* --- HDDI_ATA_SR register --------------------- */#define     HDDI_ATA_SR_ERR             0x00000001#define     HDDI_ATA_SR_DRQ             0x00000008#define     HDDI_ATA_SR_DF              0x00000020#define     HDDI_ATA_SR_DRDY            0x00000040/* --- HDDI_DMA_C register ( hardware specific ) ---------------------- */#define     HDDI_DMA_C_STARTBIT         0x00000001#define     HDDI_DMA_C_STOPBIT          0x00000002#define     HDDI_DMA_C_DMAENABLE        0x00000004#define     HDDI_DMA_C_NOTINCADDRESS    0x00000008#define     HDDI_DMA_C_READNOTWRITE     0x00000010 /* --- HDDI_DMA_SI register ( hardware specific ) --------------------- */#define     HDDI_DMA_SI_16BYTES         0x00000000#define     HDDI_DMA_SI_32BYTES         0x00000001#define     HDDI_DMA_SI_64BYTES         0x00000010#define     HDDI_DMA_SI_UNDEFINED       0x00000011 /* --- HDDI_DMA_ITS register ( hardware specific ) -------------------- */#define     HDDI_DMA_ITS_DEND           0x00000001#define     HDDI_DMA_ITS_IRQ            0x00000002#define     HDDI_DMA_ITS_DEVTERMOK      0x00000004/* --- HDDI_DMA_STA register ( hardware specific ) -------------------- */#define     HDDI_DMA_STA_DEND           0x00000001#define     HDDI_DMA_STA_IRQ            0x00000002#define     HDDI_DMA_STA_DEVTERMOK      0x00000004#define     HDDI_DMA_STA_ATADMASTATUS   0x00000700 /* --- HDDI_DMA_STA_ATADMASTATUS register ( hardware specific ) ------- */#define     HDDI_DMA_STA_ATADMASTATUS_ATAIF_INACTIVE                0x00000000#define     HDDI_DMA_STA_ATADMASTATUS_WAITING_FOR_DEV_RESPONSE      0x00000100#define     HDDI_DMA_STA_ATADMASTATUS_DEV_INITIALISED               0x00000200#define     HDDI_DMA_STA_ATADMASTATUS_DATA_BURST_INPROGRESS         0x00000300#define     HDDI_DMA_STA_ATADMASTATUS_DEV_TERM_ATTEMPT_OR_PAUSE     0x00000400#define     HDDI_DMA_STA_ATADMASTATUS_HOST_TERMINATE_ON_ERROR       0x00000500#define     HDDI_DMA_STA_ATADMASTATUS_HOST_PAUSE_FIFO_EMPTY_OR_FULL 0x00000600#define     HDDI_DMA_STA_ATADMASTATUS_DMA_COMPLETING_ABORT          0x00000700 /* --- HDDI_DMA_ITM register ( hardware specific ) -------------------- */#define     HDDI_DMA_ITM_DEND           0x00000001#define     HDDI_DMA_ITM_IRQ            0x00000002#define     HDDI_DMA_ITM_DEVTERMOK      0x00000004#endif /* ST_5514 *//* Exported Types ---------------------------------------------------------*/  typedef struct{    semaphore_t         InterruptSemaphore;    ST_Partition_t      *DriverPartition;    volatile U32        *BaseAddress;    volatile U16        *HWResetAddress;    U32                 InterruptNumber;    U32                 InterruptLevel;    STATAPI_Device_t    DeviceType;#ifdef BMDMA_ENABLE    semaphore_t         BMDMA_IntSemaphore;#endif#ifdef ST_5514    BOOL                DmaTransfer;    BOOL                DmaAborted;    U32                 StoredByteCount;#endif#if defined(ATAPI_GPDMA)    STGPDMA_Handle_t    GPDMAHandle;#endif} hal_Handle_t;#pragma ST_device(DU8)typedef volatile U8 DU8;#pragma ST_device(DU16)typedef volatile U16 DU16;#pragma ST_device(DU32)typedef volatile U32 DU32;#ifdef ST_5514/*** HDDI structures, ideally matching register layout ***//* DMA setup registers */typedef struct {    DU32 Control;    DU32 SourceAddress;    DU32 WordCount;    DU32 DMABlockSize;    DU32 CurrentAddress;                /* Read only */    DU32 CurrentByteCount;              /* Read only */} HDDI_DMASetup_t;/* PIO timing registers */typedef struct {    DU32 I;    DU32 IORDY;    DU32 WR;    DU32 RD;    DU32 WREN;    DU32 AH;    DU32 WRRE;    DU32 RDRE;} HDDI_DPIOTiming_t;/* MWDMA timing registers */typedef struct {    DU32 TD;    DU32 TH;    DU32 TJ;    DU32 TKR;    DU32 TKW;    DU32 TM;    DU32 TN;} HDDI_MWDMATiming_t;/* UDMA timing registers. Not listed in document in offset order, which is  why this struct contains the elements in a slightly different order */typedef struct {    DU32 RP;    DU32 ACK;    DU32 ENV;    DU32 TLI;    DU32 SS;    DU32 ML;    DU32 RFS;    DU32 DVS;    DU32 DVH;} HDDI_UDMATiming_t;#endif/*Exported functions---------------------------------------------------------*/BOOL hal_Init(const STATAPI_InitParams_t *params,hal_Handle_t* *HalHndl);BOOL hal_Term(hal_Handle_t *HalHndl);BOOL hal_GetCapabilities(hal_Handle_t *HalHndl,STATAPI_Capability_t *Capabilities);BOOL hal_HardReset(hal_Handle_t *HalHndl);void hal_RegOutByte(hal_Handle_t *HalHndl,ATA_Register_t regNo,U8 data);U8   hal_RegInByte (hal_Handle_t *HalHndl,ATA_Register_t regNo);void  hal_RegOutWord(hal_Handle_t *HalHndl,U16 data);U16   hal_RegInWord(hal_Handle_t *HalHndl);void ATA_BMDMA(void *Source, void *Destination, U32 Size);/* Error code is only valid if transfers are done with STGPDMA */ST_ErrorCode_t hal_RegOutBlock(hal_Handle_t *HalHndl_p, U16 *data,                                U32 Size, BOOL UseDMA);ST_ErrorCode_t hal_RegInBlock(hal_Handle_t *HalHndl_p, U16 *Data,                               U32 Size, BOOL UseDMA);void hal_EnableInts(hal_Handle_t *HalHndl);void hal_DisableInts(hal_Handle_t *HalHndl);BOOL hal_AwaitInt(hal_Handle_t *HalHndl,U32 timeout);BOOL hal_ClearInterrupt (hal_Handle_t *HalHndl);BOOL hal_GetDmaTiming(hal_Handle_t *HalHndl_p,STATAPI_DmaTiming_t *Time);BOOL hal_GetPioTiming(hal_Handle_t *HalHndl_p,STATAPI_PioTiming_t *Time);BOOL hal_SetDmaMode(hal_Handle_t *HalHndl,STATAPI_DmaMode_t mode);BOOL hal_SetPioMode(hal_Handle_t *HalHndl,STATAPI_PioMode_t mode);BOOL hal_SetDmaTiming(hal_Handle_t *HalHndl_p,STATAPI_DmaTiming_t *Time);BOOL hal_SetPioTiming(hal_Handle_t *HalHndl_p,STATAPI_PioTiming_t *Time);void hal_SetMWDMATiming(hal_Handle_t *HalHndl_p, STATAPI_MwDmaTiming_t *Timing);void hal_SetUDMATiming(hal_Handle_t *HalHndl_p,                        STATAPI_UltraDmaTiming_t *Timing);BOOL hal_DmaDataBlock(hal_Handle_t *HalHndl_p, U8 DevCtrl, U8 DevHead,                      U16 *StartAddress, U32 WordCount, U32 BufferSize,                       U32 *BytesRW, BOOL Read, BOOL *CrcError);void hal_AfterDma (hal_Handle_t *HalHndl_p);void hal_DmaPause(hal_Handle_t *HalHndl);void hal_DmaResume(hal_Handle_t *HalHndl);BOOL hal_DmaAbort(hal_Handle_t *HalHndl);#ifdef __cplusplus}#endif#endif /* _STATAPI_HAL_H */