memcpy(Time, &CurrentDmaTiming, sizeof(STATAPI_DmaTiming_t));    return FALSE;}/************************************************************************Name:   hal_GetPioTiming()Description:     retrieves the current Timing setings of the Pio ModeParameters:************************************************************************/BOOL hal_GetPioTiming (hal_Handle_t *HalHndl_p, STATAPI_PioTiming_t *Time){    if ((Time == NULL) || (HalHndl_p != The_HalHandle_p))        return TRUE;    memcpy(Time, &CurrentPioTiming, sizeof(STATAPI_PioTiming_t));        return FALSE;}BOOL hal_SetDmaTiming (hal_Handle_t *HalHndl_p, STATAPI_DmaTiming_t *Time){    BOOL Error = FALSE;        /* Check parameters */    if ((Time == NULL) || (HalHndl_p != The_HalHandle_p))        return TRUE;#ifdef ST_5514    CurrentDmaTiming = *Time;        /* Plug values into the registers */    switch (CurrentDmaMode)     {        case STATAPI_DMA_MWDMA_MODE_0:        case STATAPI_DMA_MWDMA_MODE_1:        case STATAPI_DMA_MWDMA_MODE_2:                        hal_SetMWDMATiming(HalHndl_p,                                 &Time->DmaTimingParams.MwDmaTimingParams);                        break;        case STATAPI_DMA_UDMA_MODE_0:        case STATAPI_DMA_UDMA_MODE_1:        case STATAPI_DMA_UDMA_MODE_2:        case STATAPI_DMA_UDMA_MODE_3:        case STATAPI_DMA_UDMA_MODE_4:                        hal_SetUDMATiming(HalHndl_p,                                 &Time->DmaTimingParams.UltraDmaTimingParams);                        break;        case STATAPI_DMA_NOT_SUPPORTED:        default:                        Error = TRUE;                        break;    }#else    /* Not 5514, so doesn't contain *DMA stuff */    Error = TRUE;#endif /* defined ST_5514 */    return Error;}BOOL hal_SetPioTiming (hal_Handle_t *HalHndl_p, STATAPI_PioTiming_t *Time){    BOOL Error = FALSE;    /* Basic sanity checks */    if ((HalHndl_p != The_HalHandle_p) || (Time == NULL))        return TRUE;        CurrentPioTiming = *Time;    /* Then set the appropriate registers */    SetPIOTiming(HalHndl_p->BaseAddress, Time);    return Error;}/* Worker routines, used by hal_setdmatiming and hal_setpiotiming */void hal_SetMWDMATiming(hal_Handle_t *HalHndl_p, STATAPI_MwDmaTiming_t *Timing){#ifdef ST_5514    U32 *Base = (U32 *)HalHndl_p->BaseAddress;        WriteReg((U32)Base + HDDI_MWDMA_TD, Timing->NotDIoRwAssertedT);    WriteReg((U32)Base + HDDI_MWDMA_TH, Timing->WriteDataHoldT);    WriteReg((U32)Base + HDDI_MWDMA_TJ, Timing->DIoRwToDMAckHoldT);    WriteReg((U32)Base + HDDI_MWDMA_TKR, Timing->NotDIoRNegatedT);    WriteReg((U32)Base + HDDI_MWDMA_TKW, Timing->NotDIoWNegatedT);    WriteReg((U32)Base + HDDI_MWDMA_TM, Timing->CsToNotDIoRwT);    WriteReg((U32)Base + HDDI_MWDMA_TN, Timing->CsHoldT);#endif}void hal_SetUDMATiming(hal_Handle_t *HalHndl_p, STATAPI_UltraDmaTiming_t *Timing){#ifdef ST_5514    U32 *Base = (U32 *)HalHndl_p->BaseAddress;        WriteReg((U32)Base + HDDI_UDMA_RP, Timing->MinAssertStopNegateT);    WriteReg((U32)Base + HDDI_UDMA_ACK, Timing->AckT);    WriteReg((U32)Base + HDDI_UDMA_ENV, Timing->InitEnvelopeT);    WriteReg((U32)Base + HDDI_UDMA_TLI, Timing->LimitedInterlockT);    WriteReg((U32)Base + HDDI_UDMA_SS, Timing->HostStrobeToStopSetupT);    WriteReg((U32)Base + HDDI_UDMA_ML, Timing->MinInterlockT);    WriteReg((U32)Base + HDDI_UDMA_RFS, Timing->ReadyToFinalStrobeT);    WriteReg((U32)Base + HDDI_UDMA_DVS, Timing->DataOutSetupT);    WriteReg((U32)Base + HDDI_UDMA_DVH, Timing->DataOutHoldT);#endif}void SetPIOTiming(volatile U32 *Base, STATAPI_PioTiming_t *Timing){#ifdef ST_5514    WriteReg((U32)Base + HDDI_DPIO_I, Timing->InitSequenceDelay);    WriteReg((U32)Base + HDDI_DPIO_IORDY, Timing->IoRdySetupDelay);    WriteReg((U32)Base + HDDI_DPIO_WR, Timing->WriteDelay);    WriteReg((U32)Base + HDDI_DPIO_RD, Timing->ReadDelay);    WriteReg((U32)Base + HDDI_DPIO_WREN, Timing->WriteEnableOutDelay);    WriteReg((U32)Base + HDDI_DPIO_AH, Timing->AddressHoldDelay);    WriteReg((U32)Base + HDDI_DPIO_WRRE, Timing->WriteRecoverDelay);    WriteReg((U32)Base + HDDI_DPIO_RDRE, Timing->ReadRecoverDelay);#endif}BOOL hal_DmaDataBlock(hal_Handle_t *HalHndl_p, U8 DevCtrl, U8 DevHead,                      U16 *StartAddress, U32 WordCount, U32 BufferSize,                       U32 *BytesRW, BOOL Read, BOOL *CrcError){    BOOL            Error = FALSE;#ifdef ST_5514    U32             DMAFlags = 0;    U32             BytesLeft = 0;    U8              Status;    HalHndl_p->DmaAborted = FALSE;    *CrcError = FALSE;#if defined(ATAPI_DEBUG)    if (DMAIsUDMA == TRUE)        Verbose = TRUE;    else        Verbose = FALSE;#endif    intcount = 0;        /* Ensure block is inactive, and in PIO mode to start with (which it      * should really be already).     */    if (Verbose)    {        STTBX_Print(("Transferring %i words (%i bytes)\n", WordCount,                 WordCount * 2));        STTBX_Print(("Writing %08x to %08x\n", HDDI_MODE_PIOREG,                        (U32)HalHndl_p->BaseAddress + HDDI_MODE));    }    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_MODE, HDDI_MODE_PIOREG);        HalHndl_p->StoredByteCount = 0;    HalHndl_p->DmaAborted = FALSE;        /*** Program DMA parameters ***/    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_SA, StartAddress);#if defined(HDDI_5514_CUT_2) || defined(HDDI_5514_CUT_3)    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_SI, HDDI_DMA_SI_32BYTES);#else    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_SI, HDDI_DMA_SI_64BYTES);#endif    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_WC, WordCount);    if (Verbose)     {        STTBX_Print(("Writing %08x to %08x\n", (U32)StartAddress,                 (U32)HalHndl_p->BaseAddress + HDDI_DMA_SA));        STTBX_Print(("Writing %08x to %08x\n", HDDI_DMA_SI_32BYTES,                 (U32)HalHndl_p->BaseAddress + HDDI_DMA_SI));        STTBX_Print(("Writing %08x to %08x\n", WordCount,                 (U32)HalHndl_p->BaseAddress + HDDI_DMA_WC));    }        /* Enable DMA */    DMAFlags = HDDI_DMA_C_DMAENABLE | HDDI_DMA_C_STARTBIT;    if (Read == TRUE)    {        DMAFlags |= HDDI_DMA_C_READNOTWRITE;    }    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, DMAFlags);    if (Verbose)     {        STTBX_Print(("Writing %08x to %08x\n", DMAFlags,             (U32)HalHndl_p->BaseAddress + HDDI_DMA_C));    }    /* Set this, so things (eg interrupt handler) know the transfer type */    HalHndl_p->DmaTransfer = TRUE;    /* And set the mode - this triggers the start of the transfer */    if (DMAIsUDMA == TRUE)    {        if (Verbose)         {            STTBX_Print(("Writing %08x to %08x\n", HDDI_MODE_UDMA,                    (U32)HalHndl_p->BaseAddress + HDDI_MODE));        }        WriteReg((U32)HalHndl_p->BaseAddress + HDDI_MODE, HDDI_MODE_UDMA);    }    else    {        if (Verbose)         {            STTBX_Print(("Writing %08x to %08x\n", HDDI_MODE_MWDMA,                    (U32)HalHndl_p->BaseAddress + HDDI_MODE));        }        WriteReg((U32)HalHndl_p->BaseAddress + HDDI_MODE, HDDI_MODE_MWDMA);    }    /* Remove start bit from control, else transfer terminates     * prematurely     */    DMAFlags &= ~HDDI_DMA_C_STARTBIT;    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, DMAFlags);    if (Verbose)     {        STTBX_Print(("Writing %08x to %08x\n", DMAFlags,                 (U32)HalHndl_p->BaseAddress + HDDI_DMA_C));        STTBX_Print(("DMA status: 0x%04x\n",                 ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_STA)));    }    /* Wait for results */    Error = hal_AwaitInt(HalHndl_p, INT_TIMEOUT);    if (Verbose)    {        STTBX_Print(("DMA status: 0x%04x\n",                     ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_STA)));            STTBX_Print(("Bytes remaining: %i\n",            ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_CB)));        STTBX_Print(("Interrupts received: %i\n", intcount));        if (Verbose)        {            U32 i;            for (i = 0; i < intcount; i++)                STTBX_Print(("%i %04x\n", i, inttrace[i]));            STTBX_Print(("DMA status: 0x%04x\n",                     ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_STA)));        }    }    intcount = 0;    /* Switch back to PIO/register mode, if we timed out rather than got an     * interrupt; else the interrupt handler will have done it.     */    if (Error == TRUE)    {        STTBX_Print(("Timeout0\n"));        WriteReg((U32)HalHndl_p->BaseAddress + HDDI_MODE, HDDI_MODE_PIOREG);        STTBX_Print(("Writing %08x to %08x\n", HDDI_MODE_PIOREG,                    (U32)HalHndl_p->BaseAddress + HDDI_MODE));        Status = hal_RegInByte (The_HalHandle_p, ATA_REG_STATUS);        STTBX_Print(("Status: 0x%02x\n", Status));        STTBX_Print(("DMA status: 0x%04x\n",                 ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_STA)));    }    HalHndl_p->DmaTransfer = FALSE;    DMAFlags &= ~HDDI_DMA_C_DMAENABLE;    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, DMAFlags);    if (Verbose)     {        STTBX_Print(("Writing %08x to %08x\n", DMAFlags,                 (U32)HalHndl_p->BaseAddress + HDDI_DMA_C));        STTBX_Print(("DMA status: 0x%04x\n",                 ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_STA)));        }    /* Check if an error or similar occurred */    Status = hal_RegInByte (The_HalHandle_p, ATA_REG_STATUS);    if ((Status & HDDI_ATA_SR_ERR) == HDDI_ATA_SR_ERR)    {        STTBX_Print(("Status: 0x%02x\n", Status));        Status = hal_RegInByte(The_HalHandle_p, ATA_REG_ERROR);        STTBX_Print(("Error: 0x%02x\n", Status));                    /* Set CRC flag if required, so caller can know whether or not         * retries are an option.         */        if ((Status & HDDI_ATA_ERR_ICRC) == HDDI_ATA_ERR_ICRC)        {            *CrcError = TRUE;            Error = TRUE;        }    }        /* Read bytes left to go, and work out how many were transferred. Note that     * since the register is reset to 0 when DMA is stopped or reset,     * then it will indicate no bytes went, even if they have.     */    BytesLeft = ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_CB);    #if defined(HDDI_5514_CUT_3)    /* Bug in MWDMA implementation on cut 3 - CB doesn't return true value     * when writing     */    if ((DMAIsUDMA == FALSE) && (Read == FALSE))    {        U32 temp = 2 * ((WordCount / 256) - 1);        if (BytesLeft >= temp)            BytesLeft -= temp;    }#endif        *BytesRW = (WordCount * 2) - (BytesLeft + HalHndl_p->StoredByteCount);    if (Verbose)    {        STTBX_Print(("Bytes transferred: %i\n", *BytesRW));    }        /* Believe this one is fixed in cut 3 */#if defined(HDDI_5514_CUT_2)    /* DMA aborted by user or device? */    if (HalHndl_p->DmaAborted == TRUE)    {        *BytesRW = ((*BytesRW > 64)?(*BytesRW -= 64):0);        STTBX_Print(("Adjusted bytes transferred: %i\n", *BytesRW));    }#endif    #else    Error = TRUE;#endif /* #ifdef ST_5514 */        /* Common exit */#if defined(ST_5514)    if (Verbose) { STTBX_Print(("Leaving hal_DmaDataBlock()\n")); }#endif    return Error;}void hal_AfterDma (hal_Handle_t *HalHndl_p){    /* Not required for current interfaces (all exit paths should switch     * back to PIO mode if required), but might be useful in the future.     */}/* Write to HDDI control registers to pause DMA */void hal_DmaPause (hal_Handle_t *HalHndl_p){#ifdef ST_5514    U32 ByteCount;    volatile U32 Status;    ByteCount = ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_CB);    HalHndl_p->StoredByteCount += ByteCount;    Status = ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C);    Status &= (~HDDI_DMA_C_DMAENABLE & HDDI_DMA_C_MASK);    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, Status);#if defined(HDDI_5514_CUT_3)        /* Bug in MWDMA implementation on cut 3 - CB doesn't return true value     * when writing.     */    if ((DMAIsUDMA == FALSE) && ((Status & HDDI_DMA_C_READNOTWRITE) == 0))    {        U32 temp = 2 * ((ByteCount / SECTOR_BSIZE) - 1);        HalHndl_p->StoredByteCount += temp;    }#endif    #endif}/* Write to HDDI control registers to resume DMA */void hal_DmaResume (hal_Handle_t *HalHndl_p){#ifdef ST_5514    volatile U32 Status;        Status = ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C);    Status |= HDDI_DMA_C_DMAENABLE;    WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, Status);#endif}/* Abort DMA transfer - requires transfer to have been paused first */BOOL hal_DmaAbort (hal_Handle_t *HalHndl_p){    BOOL            Error = FALSE;#ifdef ST_5514    volatile U32    Status;    HalHndl_p->StoredByteCount = 0;    Status = ReadReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C);    if ((Status & HDDI_DMA_C_DMAENABLE) != 0)    {        /* Must be paused before you can terminate. */        Error = TRUE;    }    else    {        Status |= HDDI_DMA_C_STOPBIT;        WriteReg((U32)HalHndl_p->BaseAddress + HDDI_DMA_C, Status);        HalHndl_p->DmaAborted = TRUE;    }#else    Error = TRUE;#endif        return Error;}/*end of hal_atapi.c --------------------------------------------------*/