/********************************************************************/
/*       MAC Header for KS32C50100                                  */
/*------------------------------------------------------------------*/
/*      Copyright (C) 1997 Samsung Electronics.                     */
/*------------------------------------------------------------------*/
/*                                                                  */
/*      Description : 1998-2-10 first edited for KS32C50100         */ 
/********************************************************************/
#ifndef _MAC_
#define _MAC_

#define  MAC_ADDR_SIZE         6        /* dst,src addr is 6bytes each*/ 

#define MaxRxFrameSize  	1520 // Rx Frame Max Size = 1520
#define MaxRxFrameDescriptors  	32   // Max number of Rx Frame Descriptors 
#define MaxTxFrameDescriptors  	16   // Max number of Tx Frame Descriptors
#define MaxRxFrameData         	32   // Max number of Rx Frame Data
#define MaxTxFrameData         	16   // Max number of Tx Frame Data

// TxRx Frame Descriptor 
#define	fOwnership_BDMA	0x80000000 // 0:CPU, 1:BDMA
#define	fOwnership_CPU	0x7fffffff // 0:CPU, 1:BDMA

// Tx Frame Descriptor's control bits
#define	PaddingMode		0x00
#define	NoPaddingMode		0x01
#define	NoCRCMode		0x02
#define	CRCMode			0x00
#define	MACTxIntEn		0x04
#define	LittleEndian		0x08
#define	BigEndian		0x00
#define	SourceAddrDecrement 	0x00
#define	SourceAddrIncrement 	0x10
#define	WidgetAlign00		0x00 // No Invalid bytes
#define	WidgetAlign01		0x01 // 1 Invalid byte
#define	WidgetAlign10		0x10 // 2 Invalid bytes
#define	WidgetAlign11		0x11 // 3 Invalid bytes

// Tx Frame descriptor's Status
#define	ExColl		0x0010	// Excessive Collision
#define	TxDeffer	0x0020	// Transmit deffered 
#define Paused		0x0040	// Paused : holding data transmission DMA to MAC
#define	IntTx		0x0080	// Interrupt on Transmit 
#define	Under		0x0100	// Underrun */
#define	Defer		0x0200	// Mac defers for Max_DEFERRAL:=0.32768ms 
				// for 100Mbits/s, := 3.2768ms for 10Mbits/s
#define	NCarr		0x0400	// No Carrier sense is detected during the 
				// entire transmission of a packet from SFD 
				// to CRC
#define	SQErr		0x0800	// fake collision signal didn't come from 
				// PHY for 1.6us.
#define LateColl	0x1000	// Late collision 
#define	TxPar		0x2000	// Transmit Parity Error
#define	Comp		0x4000	// MAC transmit or discards one packet
#define TxHalted	0x8000	// Transmission was halted by clearing TxEn..

// Rx Frame descriptor's Status 
#define	OvMax		0x0008	// Over Maximum Size
#define	CtlRecd		0x0020	// set if packet received is a 
				// MAC control frame.
#define	IntRx		0x0040	// Interrupt on Receive 
#define Rx10Stat	0x0080	// set if packet was received via the 
				// 10bits interface reset if packet 
				// was received via MII
#define	AlignErr	0x0100	// Alignment Error
#define	CRCErr		0x0200	// CRC error
#define	Overflow	0x0400	// MAC receive FIFO was full when it 
				// needed to store a received byte
								
#define	LongErr		0x0800	// received a frame longer than 1518bytes 
#define	RxPar		0x2000	// MAC receive FIFO has detected a parity error
#define RxGood		0x4000	// successfully received a packet with no errors
#define RxHalted	0x8000	// Transmission was halted by clearing TxEn...

// Buffered DMA Receiver Control Register 
#define	BRxBRST		0x0000F	// BDMA Rx Burst Size * BRxBRST 
				// = Burst Data Size 16
#define	BRxSTSKO	0x00020	// BDMA Rx Stop/Skip  Frame or Interrupt(=1) 
				// case of not OWNER the current Frame 
#define	BRxMAINC	0x00040	// BDMA Rx Memory Address Inc/Dec 
#define	BRxDIE		0x00080	// BDMA Rx Every Received Frame Interrupt Enable
#define	BRxNLIE		0x00100	// BDMA Rx NULL List Interrupt Enable 
#define	BRxNOIE		0x00200	// BDMA Rx Not Owner Interrupt Enable
#define	BRxMSOIE	0x00400	// BDMA Rx Maximum Size over Interrupr Enable 
#define	BRxLittle	0x00800	// BDMA Rx Big/Little Endian 
#define	BRxBig 		0x00000	// BDMA Rx Big/Little Endian
#define BRxWA01		0x01000	// BDMA Rx Word Alignment- one invalid byte 
#define BRxWA10		0x02000	// BDMA Rx Word Alignment- two invalid byte
#define BRxWA11		0x03000	// BDMA Rx Word Alignment- three invalid byte 
#define	BRxEn		0x04000	// BDMA Rx Enable
#define	BRxRS		0x08000	// BDMA Rx Reset
#define	RxEmpty		0x10000	// BDMA Rx Buffer empty interrupt 
#define	BRxEarly	0x20000	// BDMA Rx Early notify Interrupt

// Buffered DMA	Trasmit	Control Register(BDMATXCON) 
#define	BTxBRST		0x0000F	// BDMA Tx Burst Size = 16 
#define	BTxSTSKO	0x00020	// BDMA Tx Stop/Skip Frame or Interrupt in case
				// of not Owner the current frame 
#define	BTxCPIE		0x00080	// BDMA Tx Complete to send control 
				// packet Enable
#define	BTxNOIE		0x00200	// BDMA Tx Buffer Not Owner
#define	BTxEmpty	0x00400	// BDMA Tx Buffer Empty Interrupt 

// BDMA Tx buffer can be moved to the MAC Tx IO when the new frame comes in. 
#define	BTxMSL000	0x00000	// No wait to fill the BDMA 
#define	BTxMSL001	0x00800	// wait to fill 1/8 of the BDMA 
#define	BTxMSL010	0x01000	// wait to fill 2/8 of the BDMA
#define	BTxMSL011	0x01800	// wait to fill 3/8 of the BDMA
#define	BTxMSL100	0x02000	// wait to fill 4/8 of the BDMA
#define	BTxMSL101	0x02800	// wait to fill 5/8 of the BDMA
#define	BTxMSL110	0x03000	// wait to fill 6/8 of the BDMA
#define	BTxMSL111	0x03800	// wait to fill 7/8 of the BDMA
#define	BTxEn		0x04000	// BDMA Tx Enable 
#define	BTxRS		0x08000	// BDMA Rx Reset 

// BDMA Status Register 
#define	S_BRxRDF	0x00001	// BDMA Rx Done Every Received Frame 
#define	S_BRxNL		0x00002	// BDMA Rx NULL List 
#define	S_BRxNO		0x00004	// BDMA Rx Not Owner 
#define	S_BRxMSO	0x00008	// BDMA Rx Maximum Size Over 
#define	S_BRxEmpty	0x00010	// BDMA Rx Buffer Empty 
#define	S_BRxSEarly 	0x00020	// Early Notify 
#define	S_BRxFRF	0x00080 // One more frame data in BDMA receive buffer 
#define	S_BTxCCP	0x10000	// BDMA Tx Complete to send Control Packet 
#define	S_BTxNL		0x20000	// BDMA Tx Null List 
#define	S_BTxNO		0x40000	// BDMA Tx Not Owner
#define	S_BTxEmpty	0x100000// BDMA Tx Buffer Empty 

// MAC Control Register 
#define	HaltReg		0x0001	// stop transmission and reception 
				// after completion of ant current packets 
#define	HaltImm		0x0002	// Stop transmission and reception immediately 
#define	SwReset 	0x0004 	// reset all Ethernet controller state machines
				// and FIFOs 
#define	FullDup		0x0008	// allow transmission to begin while reception
				// is occurring 
#define	MACLoop		0x0010	// MAC loopback
#define	ConnM00		0x0000	// Automatic-default 
#define	ConnM01		0x0020	// Force 10Mbits endec
#define	ConnM10		0x0040	// Force MII (rate determined by MII clock 
#define	MIIOFF		0x0040	// Force MII (rate determined by MII clock 
#define	Loop10		0x0080	// Loop 10Mbps 
#define	MissRoll	0x0400	// Missed error counter rolled over 
#define	MDCOFF		0x1000	// MII Station Management Clock Off
#define	EnMissRoll	0x2000	// Interrupt when missed error counter rolls 
				// over 
#define	Link10		0x8000	// Link status 10Mbps 

// CAM control register(CAMCON) 
#define	StationAcc	0x0001	// Accept any packet with a unicast station 
				// address 
#define	GroupAcc	0x0002	// Accept any packet with multicast-group 
				// station address  
#define	BroadAcc	0x0004	// Accept any packet with a broadcast station
				// address 
#define	NegCAM		0x0008	// 0: Accept packets CAM recognizes, 
				//    reject others
				// 1: reject packets CAM recognizes, 
				//    accept others 
#define	CompEn		0x0010	// Compare Enable mode

// Transmit Control Register(MACTXCON)
#define	TxEn		0x0001	// transmit Enable 
#define TxHalt		0x0002	// Transmit Halt Request 
#define	NoPad		0x0004	// suppress Padding 
#define	NoCRC		0x0008	// Suppress CRC 
#define	FBack		0x0010	// Fast Back-off
#define	NoDef		0x0020	// Disable the defer counter
#define	SdPause		0x0040	// Send Pause
#define	MII10En		0x0080	// MII 10Mbps mode enable
#define	EnUnder		0x0100	// Enable Underrun
#define	EnDefer		0x0200	// Enable Deferral
#define	EnNCarr		0x0400	// Enable No Carrier 
#define	EnExColl	0x0800	// interrupt if 16 collision occur 
				// in the same packet 
#define EnLateColl	0x1000	// interrupt if collision occurs after 
				// 512 bit times(64 bytes times) 
#define	EnTxPar		0x2000	// interrupt if the MAC transmit FIFO 
				// has a parity error 
#define	EnComp		0x4000	// interrupt when the MAC transmits or 
				// discards one packet 

// Transmit Status Register(MACTXSTAT)
#define	ExColl		0x0010	// Excessive collision 
#define	TxDeffered	0x0020	// set if 16 collisions occur for same packet
#define	Paused		0x0040	// packet waited because of pause during 
				// transmission 
#define	IntTx		0x0080	// set if transmission of packet causes an 
				// interrupt condiftion 
#define	Under		0x0100	// MAC transmit FIFO becomes empty during 
				// transmission 
#define Defer		0x0200	// MAC defers for MAC deferral 
#define	NCarr		0x0400	// No carrier sense detected during the 
				// transmission of a packet 
#define	SQE		0x0800	// Signal Quality Error
#define	LateColl	0x1000	// a collision occures after 512 bit times 
#define	TxPar		0x2000	// MAC transmit FIFO has detected a parity error
#define	Comp		0x4000	// MAC transmit or discards one packet 
#define	TxHalted	0x8000	// Transmission was halted by clearing 
				// TxEn or Halt immedite 

// Receive Control Register (MACRXCON) 
#define	RxEn		0x0001
#define	RxHalt		0x0002
#define	LongEn		0x0004
#define	ShortEn		0x0008
#define	StripCRC	0x0010
#define	PassCtl		0x0020
#define	IgnoreCRC	0x0040
#define	EnAlign		0x0100
#define	EnCRCErr	0x0200
#define	EnOver		0x0400
#define	EnLongErr	0x0800
#define	EnRxPar		0x2000
#define	EnGood		0x4000

// Receive Status Register(MACRXSTAT)
#define MCtlRecd	0x0020
#define	MIntRx		0x0040
#define	MRx10Stat	0x0080
#define	MAllignErr	0x0100
#define	MCRCErr		0x0200
#define	MOverflow	0x0400
#define	MLongErr	0x0800
#define	MRxPar		0x2000
#define	MRxGood		0x4000
#define	MRxHalted	0x8000


// Tx/Rx common descriptor structure