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;;;;	This Part is about Memory Define	   ;;;;
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; Internal SRAM area

                ^       0x3FE0000
InterSramArea   #       8192

		
SystemStackAdr	EQU	0x13f0000 	;Stack Area: 0x13f0000~0x13fffff
USR_STACK_SIZE   	EQU    	1024 
UDF_STACK_SIZE   	EQU    	512 
ABT_STACK_SIZE   	EQU    	512 
IRQ_STACK_SIZE   	EQU    	2048 
FIQ_STACK_SIZE   	EQU    	2048 
SUP_STACK_SIZE   	EQU    	2048 

USR_STACK	EQU	SystemStackAdr
UDF_STACK        	EQU    	SystemStackAdr + USR_STACK_SIZE  
ABT_STACK   	EQU	UDF_STACK + UDF_STACK_SIZE
IRQ_STACK	EQU	ABT_STACK + ABT_STACK_SIZE
FIQ_STACK        	EQU    	IRQ_STACK + IRQ_STACK_SIZE
SUP_STACK	EQU    	FIQ_STACK + FIQ_STACK_SIZE


DRAM_BASE       	EQU     0x00400000
DRAM_LIMIT      	EQU     0x01400000
;-------------------------------------------------
;ExceptionSize    EQU     0x50            ; exception vector addr pointer space
;SysStackSize     EQU     1024 * 8        ; Define 8K System stack
;ExceptionTable   EQU     DRAM_BASE + ExceptionSize

;/* EXCEPTION HANDLER VECTOR TABLE */
;	        ^	DRAM_BASE
;HandleReset	#	4
;HandleUndef	#	4
;HandleSwi   	#	4
;HandlePrefetch	#	4
;HandleAbort	#	4
;HandleReserv	#	4
;HandleIrq   	#	4
;HandleFiq	#	4

;/* SYSTEM USER CODE AREA  */

;		^	DRAM_BASE+ExceptionSize ;=0x1000050
;UserCodeArea	#	4


;/*************************************************************************/
;/* DRAM Memory Bank 1 area(NonCacheable region) */
;/*  for DMA(Direct Memory Access) function      */
;/*************************************************************************/

;                ^      0x1400000
;DmaCodeArea     #      4

;                ^      0x1700000
;UserFreeArea    #      4 


;***************************************************************************
;=		MEM BUS WIDTH REG		
;***************************************************************************
DSR0  			EQU  3:SHL:0		; ROM0 :32 bits	
DSR1  			EQU  0:SHL:2	      	; ROM1 :disable  	
DSR2  			EQU  0:SHL:4	    	; ROM2 :disable
DSR3  			EQU  0:SHL:6	     	; ROM3 :disable
DSR4  			EQU  0:SHL:8 		; ROM4 :disable
DSR5  			EQU  0:SHL:10		; ROM5 :disable

DSD0  			EQU  3:SHL:12		; DRAM0:32 bits
DSD1  			EQU  0:SHL:14		; DRAM1:disable
DSD2  			EQU  0:SHL:16              ; DRAM2:disable
DSD3  			EQU  0:SHL:18              ; DRAM3:disable

DSX0  			EQU  0:SHL:20		; EXTIO0:disable
DSX1  			EQU  0:SHL:22	         ; EXTIO1:disable
DSX2  			EQU  0:SHL:24        	; EXTIO2:disable
DSX3  			EQU  0:SHL:26              ; EXTIO3:disable

rEXTDBWTH	 	EQU  (DSR0+DSR1+DSR2+DSR3+DSR4+DSR5+DSD0+DSD1+DSD2+DSD3+DSX0+DSX1+DSX2+DSX3) ;=0x00003003

;************************************************************************************
;=		ROM0,1,2,3,4,5 REG		=
;************************************************************************************

;---ROMCON0 : ROM Bank0 Control register---
PMC0            	EQU  0x0:SHL:0    	       	; 0x0=Normal ROM, 0x1=4Word Page 
                                            	       	; 0x2=8Word Page, 0x3=16Word Page
Tpa0            	EQU  0x0:SHL:2 		       	; 0x0=5Cycle, 0x1=2Cycle
                          	                         	; 0x2=3Cycle, 0x3=4Cycle 
Tacc0          	EQU  0x6:SHL:4		       	; 0x0=Disable, 0x1=2Cycle
                  	                         	; 0x2=3Cycle, 0x3=4Cycle
                        	            	       	; 0x4=5Cycle, 0x5=6Cycle
                                	    	       	; 0x6=7Cycle, 0x7=Reserved

ROMBasePtr0     	EQU  0x0:SHL:10		       	;=0x0000000  0M
ROMEndPtr0      	EQU  0x40:SHL:20	       		;=0x0400000  4M 

rROMCON0   	EQU  ROMEndPtr0+ROMBasePtr0+Tacc0+Tpa0+PMC0   ;=0x04000060

;/--- ROMCON1,2,3,4,5 : ROM Bank1,2,3,4,5 Control register ---
rROMCON1		EQU	0x60
rROMCON2 	EQU  	0x60
rROMCON3   	EQU  	0x60
rROMCON4   	EQU  	0x60
rROMCON5   	EQU  	0x60

;***************************************************************************************
;=		SDROM0,1,2,3 REG		=
;***************************************************************************************
;/* ->SDRAMCON0 : RAM Bank0 control register */
DRAMBasePtr0   	 	EQU	0x40:SHL:10            ;=0x00400000   4M
DRAMEndPtr0        	EQU  	0x140:SHL:20           ;=0x01400000   20M
SRAS2CASDelay0      	EQU  	1                      ;(Trc)0=1cycle,1=2cycle
SRASPrechargeTime0  	EQU  	3                      ;(Trp)0=1cycle ~ 3=4clcyle
SNoColumnAddr0      	EQU  	0                      ;0=8bit,1=9bit,2=10bit,3=11bits
SCAN0               	EQU  	SNoColumnAddr0:SHL:30
STrc0               	EQU  	SRAS2CASDelay0:SHL:7
STrp0               	EQU  	SRASPrechargeTime0:SHL:8

rSDRAMCON0	    	EQU	SCAN0+DRAMEndPtr0+DRAMBasePtr0+STrp0+STrc0  ;=0x14010380


;/* ->SDRAMCON1,2,3 : RAM Bank1 control register */
rSDRAMCON1	   	EQU  	0x0
rSDRAMCON2     	   	EQU  	0x0
rSDRAMCON3   	   	EQU  	0x0

;/* -> REFEXTCON : External I/O & Memory Refresh cycle Control Register */
ExtIOBase          	EQU	0x360      ; 
VSF		  	EQU	0x1:SHL:15 ; Accessiable to memory bank
Refresh		   	EQU	0X1:SHL:16 ; Enable
Trc                	EQU  3:SHL:17   ; 0=1cycle, 1=2cycle, 2=3cycle,
                                   ; 3=4cycle, 4=5cycle
RefCycle      	   	EQU   8   ;Unit [us], 4k refresh 64ms
RefCycleValue  	   	EQU   ((2048+1-(RefCycle*fMCLK)):SHL:21)

rSREFEXTCON     	   	EQU   RefCycleValue+Trc+Refresh+VSF+ExtIOBase

;**************************************************************************************
  END