?? acpi.c
字號:
/* * Advanced Configuration and Power Interface * * Based on 'ACPI Specification 1.0b' February 2, 1999 and * 'IA-64 Extensions to ACPI Specification' Revision 0.6 * * Copyright (C) 1999 VA Linux Systems * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com> * Copyright (C) 2000 Hewlett-Packard Co. * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com> * Copyright (C) 2000 Intel Corp. * Copyright (C) 2000,2001 J.I. Lee <jung-ik.lee@intel.com> * ACPI based kernel configuration manager. * ACPI 2.0 & IA64 ext 0.71 */#include <linux/config.h>#include <linux/init.h>#include <linux/kernel.h>#include <linux/sched.h>#include <linux/smp.h>#include <linux/string.h>#include <linux/types.h>#include <linux/irq.h>#ifdef CONFIG_SERIAL_ACPI#include <linux/acpi_serial.h>#endif#include <asm/acpi-ext.h>#include <asm/acpikcfg.h>#include <asm/efi.h>#include <asm/io.h>#include <asm/iosapic.h>#include <asm/machvec.h>#include <asm/page.h>#undef ACPI_DEBUG /* Guess what this does? *//* global array to record platform interrupt vectors for generic int routing */int platform_irq_list[ACPI_MAX_PLATFORM_IRQS];/* These are ugly but will be reclaimed by the kernel */int __initdata available_cpus;int __initdata total_cpus;void (*pm_idle) (void);void (*pm_power_off) (void);asm (".weak iosapic_register_irq");asm (".weak iosapic_register_legacy_irq");asm (".weak iosapic_register_platform_irq");asm (".weak iosapic_init");asm (".weak iosapic_version");const char *acpi_get_sysname (void){ /* the following should go away once we have an ACPI parser: */#ifdef CONFIG_IA64_GENERIC return "hpsim";#else# if defined (CONFIG_IA64_HP_SIM) return "hpsim";# elif defined (CONFIG_IA64_SGI_SN1) return "sn1";# elif defined (CONFIG_IA64_SGI_SN2) return "sn2";# elif defined (CONFIG_IA64_DIG) return "dig";# else# error Unknown platform. Fix acpi.c.# endif#endif}/* * Interrupt routing API for device drivers. * Provides the interrupt vector for a generic platform event * (currently only CPEI implemented) */intacpi_request_vector(u32 int_type){ int vector = -1; if (int_type < ACPI_MAX_PLATFORM_IRQS) { /* correctable platform error interrupt */ vector = platform_irq_list[int_type]; } else printk("acpi_request_vector(): invalid interrupt type\n"); return vector;}/* * Configure legacy IRQ information. */static void __initacpi_legacy_irq (char *p){ acpi_entry_int_override_t *legacy = (acpi_entry_int_override_t *) p; unsigned long polarity = 0, edge_triggered = 0; /* * If the platform we're running doesn't define * iosapic_register_legacy_irq(), we ignore this info... */ if (!iosapic_register_legacy_irq) return; switch (legacy->flags) { case 0x5: polarity = 1; edge_triggered = 1; break; case 0x7: polarity = 0; edge_triggered = 1; break; case 0xd: polarity = 1; edge_triggered = 0; break; case 0xf: polarity = 0; edge_triggered = 0; break; default: printk(" ACPI Legacy IRQ 0x%02x: Unknown flags 0x%x\n", legacy->isa_irq, legacy->flags); break; } iosapic_register_legacy_irq(legacy->isa_irq, legacy->pin, polarity, edge_triggered);}/* * ACPI 2.0 tables parsing functions */static unsigned longreadl_unaligned(void *p){ unsigned long ret; memcpy(&ret, p, sizeof(long)); return ret;}/* * Identify usable CPU's and remember them for SMP bringup later. */static void __initacpi20_lsapic (char *p){ int add = 1; acpi20_entry_lsapic_t *lsapic = (acpi20_entry_lsapic_t *) p; printk(" CPU %.04x:%.04x: ", lsapic->eid, lsapic->id); if ((lsapic->flags & LSAPIC_ENABLED) == 0) { printk("disabled.\n"); add = 0; }#ifdef CONFIG_SMP smp_boot_data.cpu_phys_id[total_cpus] = -1;#endif if (add) { available_cpus++; printk("available");#ifdef CONFIG_SMP smp_boot_data.cpu_phys_id[total_cpus] = (lsapic->id << 8) | lsapic->eid; if (hard_smp_processor_id() == smp_boot_data.cpu_phys_id[total_cpus]) printk(" (BSP)");#endif printk(".\n"); } total_cpus++;}/* * Extract iosapic info from madt (again) to determine which iosapic * this platform interrupt resides in */static int __initacpi20_which_iosapic (int global_vector, acpi_madt_t *madt, u32 *irq_base, char **iosapic_address){ acpi_entry_iosapic_t *iosapic; char *p, *end; int ver, max_pin; p = (char *) (madt + 1); end = p + (madt->header.length - sizeof(acpi_madt_t)); while (p < end) { switch (*p) { case ACPI20_ENTRY_IO_SAPIC: /* collect IOSAPIC info for platform int use later */ iosapic = (acpi_entry_iosapic_t *)p; *irq_base = iosapic->irq_base; *iosapic_address = ioremap(iosapic->address, 0); /* is this the iosapic we're looking for? */ ver = iosapic_version(*iosapic_address); max_pin = (ver >> 16) & 0xff; if ((global_vector - *irq_base) <= max_pin) return 0; /* found it! */ break; default: break; } p += p[1]; } return 1;}/* * Info on platform interrupt sources: NMI, PMI, INIT, etc. */static void __initacpi20_platform (char *p, acpi_madt_t *madt){ int vector; u32 irq_base; char *iosapic_address; unsigned long polarity = 0, trigger = 0; acpi20_entry_platform_src_t *plat = (acpi20_entry_platform_src_t *) p; printk("PLATFORM: IOSAPIC %x -> Vector %x on CPU %.04u:%.04u\n", plat->iosapic_vector, plat->global_vector, plat->eid, plat->id); /* record platform interrupt vectors for generic int routing code */ if (!iosapic_register_platform_irq) { printk("acpi20_platform(): no ACPI platform IRQ support\n"); return; } /* extract polarity and trigger info from flags */ switch (plat->flags) { case 0x5: polarity = 1; trigger = 1; break; case 0x7: polarity = 0; trigger = 1; break; case 0xd: polarity = 1; trigger = 0; break; case 0xf: polarity = 0; trigger = 0; break; default: printk("acpi20_platform(): unknown flags 0x%x\n", plat->flags); break; } /* which iosapic does this IRQ belong to? */ if (acpi20_which_iosapic(plat->global_vector, madt, &irq_base, &iosapic_address)) { printk("acpi20_platform(): I/O SAPIC not found!\n"); return; } /* * get vector assignment for this IRQ, set attributes, and program the IOSAPIC * routing table */ vector = iosapic_register_platform_irq(plat->int_type, plat->global_vector, plat->iosapic_vector, plat->eid, plat->id, polarity, trigger, irq_base, iosapic_address); platform_irq_list[plat->int_type] = vector;}/* * Override the physical address of the local APIC in the MADT stable header. */static void __initacpi20_lapic_addr_override (char *p){ acpi20_entry_lapic_addr_override_t * lapic = (acpi20_entry_lapic_addr_override_t *) p; if (lapic->lapic_address) { iounmap((void *)ipi_base_addr); ipi_base_addr = (unsigned long) ioremap(lapic->lapic_address, 0); printk("LOCAL ACPI override to 0x%lx(p=0x%lx)\n", ipi_base_addr, lapic->lapic_address); }}/* * Parse the ACPI Multiple APIC Description Table */static void __initacpi20_parse_madt (acpi_madt_t *madt){ acpi_entry_iosapic_t *iosapic = NULL; acpi20_entry_lsapic_t *lsapic = NULL; char *p, *end; int i; /* Base address of IPI Message Block */ if (madt->lapic_address) { ipi_base_addr = (unsigned long) ioremap(madt->lapic_address, 0); printk("Lapic address set to 0x%lx\n", ipi_base_addr); } else printk("Lapic address set to default 0x%lx\n", ipi_base_addr); p = (char *) (madt + 1); end = p + (madt->header.length - sizeof(acpi_madt_t)); /* Initialize platform interrupt vector array */ for (i = 0; i < ACPI_MAX_PLATFORM_IRQS; i++) platform_irq_list[i] = -1; /* * Split-up entry parsing to ensure ordering. */ while (p < end) { switch (*p) { case ACPI20_ENTRY_LOCAL_APIC_ADDR_OVERRIDE: printk("ACPI 2.0 MADT: LOCAL APIC Override\n"); acpi20_lapic_addr_override(p); break; case ACPI20_ENTRY_LOCAL_SAPIC: printk("ACPI 2.0 MADT: LOCAL SAPIC\n"); lsapic = (acpi20_entry_lsapic_t *) p; acpi20_lsapic(p); break; case ACPI20_ENTRY_IO_SAPIC: iosapic = (acpi_entry_iosapic_t *) p; if (iosapic_init) /* * The PCAT_COMPAT flag indicates that the system has a * dual-8259 compatible setup. */ iosapic_init(iosapic->address, iosapic->irq_base,#ifdef CONFIG_ITANIUM 1 /* fw on some Itanium systems is broken... */#else (madt->flags & MADT_PCAT_COMPAT)#endif ); break; case ACPI20_ENTRY_PLATFORM_INT_SOURCE: printk("ACPI 2.0 MADT: PLATFORM INT SOURCE\n"); acpi20_platform(p, madt); break; case ACPI20_ENTRY_LOCAL_APIC:
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -