// -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- #define AT91C_RTC_SEC         ((unsigned int) 0x7F <<  0) // (RTC) Current Second#define AT91C_RTC_MIN         ((unsigned int) 0x7F <<  8) // (RTC) Current Minute#define AT91C_RTC_HOUR        ((unsigned int) 0x1F << 16) // (RTC) Current Hour#define AT91C_RTC_AMPM        ((unsigned int) 0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator// -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- #define AT91C_RTC_CENT        ((unsigned int) 0x3F <<  0) // (RTC) Current Century#define AT91C_RTC_YEAR        ((unsigned int) 0xFF <<  8) // (RTC) Current Year#define AT91C_RTC_MONTH       ((unsigned int) 0x1F << 16) // (RTC) Current Month#define AT91C_RTC_DAY         ((unsigned int) 0x7 << 21) // (RTC) Current Day#define AT91C_RTC_DATE        ((unsigned int) 0x3F << 24) // (RTC) Current Date// -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- #define AT91C_RTC_SECEN       ((unsigned int) 0x1 <<  7) // (RTC) Second Alarm Enable#define AT91C_RTC_MINEN       ((unsigned int) 0x1 << 15) // (RTC) Minute Alarm#define AT91C_RTC_HOUREN      ((unsigned int) 0x1 << 23) // (RTC) Current Hour// -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- #define AT91C_RTC_MONTHEN     ((unsigned int) 0x1 << 23) // (RTC) Month Alarm Enable#define AT91C_RTC_DATEEN      ((unsigned int) 0x1 << 31) // (RTC) Date Alarm Enable// -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- #define AT91C_RTC_ACKUPD      ((unsigned int) 0x1 <<  0) // (RTC) Acknowledge for Update#define AT91C_RTC_ALARM       ((unsigned int) 0x1 <<  1) // (RTC) Alarm Flag#define AT91C_RTC_SECEV       ((unsigned int) 0x1 <<  2) // (RTC) Second Event#define AT91C_RTC_TIMEV       ((unsigned int) 0x1 <<  3) // (RTC) Time Event#define AT91C_RTC_CALEV       ((unsigned int) 0x1 <<  4) // (RTC) Calendar event// -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- #define AT91C_RTC_NVTIM       ((unsigned int) 0x1 <<  0) // (RTC) Non valid Time#define AT91C_RTC_NVCAL       ((unsigned int) 0x1 <<  1) // (RTC) Non valid Calendar#define AT91C_RTC_NVTIMALR    ((unsigned int) 0x1 <<  2) // (RTC) Non valid time Alarm#define AT91C_RTC_NVCALALR    ((unsigned int) 0x1 <<  3) // (RTC) Nonvalid Calendar Alarm// *****************************************************************************//              SOFTWARE API DEFINITION  FOR System Timer Interface// *****************************************************************************typedef struct _AT91S_ST {	AT91_REG	 ST_CR; 	// Control Register	AT91_REG	 ST_PIMR; 	// Period Interval Mode Register	AT91_REG	 ST_WDMR; 	// Watchdog Mode Register	AT91_REG	 ST_RTMR; 	// Real-time Mode Register	AT91_REG	 ST_SR; 	// Status Register	AT91_REG	 ST_IER; 	// Interrupt Enable Register	AT91_REG	 ST_IDR; 	// Interrupt Disable Register	AT91_REG	 ST_IMR; 	// Interrupt Mask Register	AT91_REG	 ST_RTAR; 	// Real-time Alarm Register	AT91_REG	 ST_CRTR; 	// Current Real-time Register} AT91S_ST, *AT91PS_ST;// -------- ST_CR : (ST Offset: 0x0) System Timer Control Register -------- #define AT91C_ST_WDRST        ((unsigned int) 0x1 <<  0) // (ST) Watchdog Timer Restart// -------- ST_PIMR : (ST Offset: 0x4) System Timer Period Interval Mode Register -------- #define AT91C_ST_PIV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart// -------- ST_WDMR : (ST Offset: 0x8) System Timer Watchdog Mode Register -------- #define AT91C_ST_WDV          ((unsigned int) 0xFFFF <<  0) // (ST) Watchdog Timer Restart#define AT91C_ST_RSTEN        ((unsigned int) 0x1 << 16) // (ST) Reset Enable#define AT91C_ST_EXTEN        ((unsigned int) 0x1 << 17) // (ST) External Signal Assertion Enable// -------- ST_RTMR : (ST Offset: 0xc) System Timer Real-time Mode Register -------- #define AT91C_ST_RTPRES       ((unsigned int) 0xFFFF <<  0) // (ST) Real-time Timer Prescaler Value// -------- ST_SR : (ST Offset: 0x10) System Timer Status Register -------- #define AT91C_ST_PITS         ((unsigned int) 0x1 <<  0) // (ST) Period Interval Timer Interrupt#define AT91C_ST_WDOVF        ((unsigned int) 0x1 <<  1) // (ST) Watchdog Overflow#define AT91C_ST_RTTINC       ((unsigned int) 0x1 <<  2) // (ST) Real-time Timer Increment#define AT91C_ST_ALMS         ((unsigned int) 0x1 <<  3) // (ST) Alarm Status// -------- ST_IER : (ST Offset: 0x14) System Timer Interrupt Enable Register -------- // -------- ST_IDR : (ST Offset: 0x18) System Timer Interrupt Disable Register -------- // -------- ST_IMR : (ST Offset: 0x1c) System Timer Interrupt Mask Register -------- // -------- ST_RTAR : (ST Offset: 0x20) System Timer Real-time Alarm Register -------- #define AT91C_ST_ALMV         ((unsigned int) 0xFFFFF <<  0) // (ST) Alarm Value Value// -------- ST_CRTR : (ST Offset: 0x24) System Timer Current Real-time Register -------- #define AT91C_ST_CRTV         ((unsigned int) 0xFFFFF <<  0) // (ST) Current Real-time Value// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Power Management Controler// *****************************************************************************typedef struct _AT91S_PMC {	AT91_REG	 PMC_SCER; 	// System Clock Enable Register	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register	AT91_REG	 PMC_SCSR; 	// System Clock Status Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register	AT91_REG	 Reserved1[5]; 	// 	AT91_REG	 PMC_MCKR; 	// Master Clock Register	AT91_REG	 Reserved2[3]; 	// 	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register	AT91_REG	 PMC_IER; 	// Interrupt Enable Register	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register	AT91_REG	 PMC_SR; 	// Status Register	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register} AT91S_PMC, *AT91PS_PMC;// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- #define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  1) // (PMC) USB Device Port Clock#define AT91C_PMC_MCKUDP      ((unsigned int) 0x1 <<  2) // (PMC) USB Device Port Master Clock Automatic Disable on Suspend#define AT91C_PMC_UHP         ((unsigned int) 0x1 <<  4) // (PMC) USB Host Port Clock#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK4        ((unsigned int) 0x1 << 12) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK5        ((unsigned int) 0x1 << 13) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK6        ((unsigned int) 0x1 << 14) // (PMC) Programmable Clock Output#define AT91C_PMC_PCK7        ((unsigned int) 0x1 << 15) // (PMC) Programmable Clock Output// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- #define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected#define 	AT91C_PMC_CSS_PLLA_CLK             ((unsigned int) 0x2) // (PMC) Clock from PLL A is selected#define 	AT91C_PMC_CSS_PLLB_CLK             ((unsigned int) 0x3) // (PMC) Clock from PLL B is selected#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64#define AT91C_PMC_MDIV        ((unsigned int) 0x3 <<  8) // (PMC) Master Clock Division#define 	AT91C_PMC_MDIV_1                    ((unsigned int) 0x0 <<  8) // (PMC) The master clock and the processor clock are the same#define 	AT91C_PMC_MDIV_2                    ((unsigned int) 0x1 <<  8) // (PMC) The processor clock is twice as fast as the master clock#define 	AT91C_PMC_MDIV_3                    ((unsigned int) 0x2 <<  8) // (PMC) The processor clock is three times faster than the master clock#define 	AT91C_PMC_MDIV_4                    ((unsigned int) 0x3 <<  8) // (PMC) The processor clock is four times faster than the master clock// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- #define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask#define AT91C_PMC_LOCKA       ((unsigned int) 0x1 <<  1) // (PMC) PLL A Status/Enable/Disable/Mask#define AT91C_PMC_LOCKB       ((unsigned int) 0x1 <<  2) // (PMC) PLL B Status/Enable/Disable/Mask#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK4RDY     ((unsigned int) 0x1 << 12) // (PMC) PCK4_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK5RDY     ((unsigned int) 0x1 << 13) // (PMC) PCK5_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK6RDY     ((unsigned int) 0x1 << 14) // (PMC) PCK6_RDY Status/Enable/Disable/Mask#define AT91C_PMC_PCK7RDY     ((unsigned int) 0x1 << 15) // (PMC) PCK7_RDY Status/Enable/Disable/Mask// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- // *****************************************************************************//              SOFTWARE API DEFINITION  FOR Clock Generator Controler// *****************************************************************************typedef struct _AT91S_CKGR {	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register	AT91_REG	 CKGR_PLLAR; 	// PLL A Register	AT91_REG	 CKGR_PLLBR; 	// PLL B Register} AT91S_CKGR, *AT91PS_CKGR;// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- #define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable#define AT91C_CKGR_OSCTEST    ((unsigned int) 0x1 <<  1) // (CKGR) Oscillator Test#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- #define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- #define AT91C_CKGR_DIVA       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected#define 	AT91C_CKGR_DIVA_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0#define 	AT91C_CKGR_DIVA_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLACOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL A Counter#define AT91C_CKGR_OUTA       ((unsigned int) 0x3 << 14) // (CKGR) PLL A Output Frequency Range#define 	AT91C_CKGR_OUTA_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLA datasheet#define 	AT91C_CKGR_OUTA_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLA datasheet#define 	AT91C_CKGR_OUTA_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLA datasheet#define 	AT91C_CKGR_OUTA_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLA datasheet#define AT91C_CKGR_MULA       ((unsigned int) 0x7FF << 16) // (CKGR) PLL A Multiplier#define AT91C_CKGR_SRCA       ((unsigned int) 0x1 << 29) // (CKGR) PLL A Source// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- #define AT91C_CKGR_DIVB       ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected#define 	AT91C_CKGR_DIVB_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0#define 	AT91C_CKGR_DIVB_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed#define AT91C_CKGR_PLLBCOUNT  ((unsigned int) 0x3F <<  8) // (CKGR) PLL B Counter#define AT91C_CKGR_OUTB       ((unsigned int) 0x3 << 14) // (CKGR) PLL B Output Frequency Range#define 	AT91C_CKGR_OUTB_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLLB datasheet#define 	AT91C_CKGR_OUTB_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLLB datasheet#define 	AT91C_CKGR_OUTB_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLLB datasheet#define 	AT91C_CKGR_OUTB_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLLB datasheet#define AT91C_CKGR_MULB       ((unsigned int) 0x7FF << 16) // (CKGR) PLL B Multiplier#define AT91C_CKGR_USB_96M    ((unsigned int) 0x1 << 28) // (CKGR) Divider for USB Ports#define AT91C_CKGR_USB_PLL    ((unsigned int) 0x1 << 29) // (CKGR) PLL Use// *****************************************************************************//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler// *****************************************************************************typedef struct _AT91S_PIO {	AT91_REG	 PIO_PER; 	// PIO Enable Register	AT91_REG	 PIO_PDR; 	// PIO Disable Register	AT91_REG	 PIO_PSR; 	// PIO Status Register	AT91_REG	 Reserved0[1]; 	// 	AT91_REG	 PIO_OER; 	// Output Enable Register	AT91_REG	 PIO_ODR; 	// Output Disable Registerr