/****************************************************************
*	funpwm.c					See funlib.h for instuctions	*
*	Don Luebbe                  about using this file.          *
*	10/12/02                                                    *
*																*
*	This file defines two PWM functions: initPWM() and setPWM().*
*	initPWM() initializes a pair of pins as PWM outputs and must*
*	be called for each set of pins.  The output come in pairs   *
*	because there are two pins available for each compare 		*
*	register.  The pins in a pair are inverses of each other.   *
*	setPWM() accepts one of a pair's pin numbers and updates the*
*	corresponding compare register with the desired duty cycle. *
*	It should be used as needed to update a given pwm output.	*
*																*
*	Example:	main()                                          *
*				{                                               *
*					initPWM(1,2000);                            *
*					...                                         *
*					while(1)                                    *
*					{                                           *
*						dutycycle = ...;                        *
*						setPWM(1,dutycycle);                    *
*					}                                           *
*				}                                               *
*				This code sets up PWM1 with a 20 kHz carrier 	*
*				frequency and updates the dutycycle everytime	*
*				through the while loop.							*
****************************************************************/

#include        "f2407_c.h"
#include        "funlib.h"
#include		<math.h>

int initPWM(int channel, int period)
{
	if ((channel < 1) || (channel > 12))
	{
		return -1;			/* returns -1 if channel is not valid */
	}   
	
	if (channel < 7)        /* chooses between event managers */
	{
    	*T1CON = 0x0000;      /* disable timer 1 */
    	*GPTCONA = 0x0000;    /* configure GPTCONA */
		/*     
 		bit 15        0:      reserved
 		bit 14        0:      T2STAT, read-only
 		bit 13        0:      T1STAT, read-only
 		bit 12-11     00:     reserved
		bit 10-9      00:     T2TOADC, 00 = no timer2 event starts ADC
 		bit 8-7       00:     T1TOADC, 00 = no timer1 event starts ADC
 		bit 6         0:      TCOMPOE, 0 = Hi-z all timer compare outputs
 		bit 5-4       00:     reserved
 		bit 3-2       00:     T2PIN, 00 = forced low
 		bit 1-0       00:     T1PIN, 00 = forced low
		*/

    	*T1CNT = 0x0000;      /* clear timer counter */
    	*T1PR = period;       /* set timer period */
    	*DBTCONA = 0x0000;    /* deadband units off */
    
    	switch(channel)
    	{
    		case 1: *MCRA = *MCRA | 0x0040;
    				*ACTRA = (*ACTRA & ~0x0003);
    				*ACTRA = (*ACTRA | 0x0002);
    				*CMPR1 = 0;		/* set PWM1/2 duty cycle */
    				break;
    			
    		case 2: *MCRA = *MCRA | 0x0080;
    				*ACTRA = *ACTRA & ~0x000C;
    				*ACTRA = *ACTRA | 0x0008;
    				*CMPR1 = 0;
	    			break;
    				
	    	case 3: *MCRA = *MCRA | 0x0100;
	    			*ACTRA = *ACTRA & ~0x0030;
    				*ACTRA = *ACTRA | 0x0020;
    				*CMPR2 = 0;     /* set PWM3/4 duty cycle */
    				break;
    			
	    	case 4: *MCRA = *MCRA | 0x0200;
	    			*ACTRA = *ACTRA & ~0x00C0;
    				*ACTRA = *ACTRA | 0x0080;
    				*CMPR2 = 0;
    				break;
    			
    		case 5: *MCRA = *MCRA | 0x0400;
    				*ACTRA = *ACTRA & ~0x0300;
    				*ACTRA = *ACTRA | 0x0200;
    				*CMPR3 = 0;     /* set PWM5/6 duty cycle */
    				break;
    			
    		case 6: *MCRA = *MCRA | 0x0800;
    		        *ACTRA = *ACTRA & ~0x0C00;
    				*ACTRA = *ACTRA | 0x0800;
    				*CMPR3 = 0;
    				break;
    
			/*
 			bit 15        space vector dir is CCW (don't care)
	 		bit 14-12     basic space vector is 000 (dont' care)
 			bit 11-10     PWM6/IOPB3 pin activity
 			bit 9-8       PWM5/IOPB2 pin activity
	 		bit 7-6       PWM4/IOPB1 pin activity
	 		bit 5-4       PWM3/IOPB0 pin activity
	 		bit 3-2       PWM2/IOPA7 pin activity
 			bit 1-0       PWM1/IOPA6 pin activity
			*/
	    }
     
    	*COMCONA = 0x8200;    /* configure COMCONA register */
		/*
 		bit 15        1:      1 = enable compare operation
	 	bit 14-13     00:     00 = reload CMPRx regs on timer 1 underflow
	 	bit 12        0:      0 = space vector disabled
	 	bit 11-10     00:     00 = reload ACTR on timer 1 underflow
	 	bit 9         1:      1 = enable PWM pins
	 	bit 8-0       0's:    reserved
		*/
    
    	*T1CON = 0xD048;      /* configure T1CON register */
		/*     
	 	bit 15-14     00:     stop immediately on emulator suspend
	 	bit 13        0:      reserved
 		bit 12-11     10:     10 = continous-up count mode
	 	bit 10-8      000:    000 = x/1 prescaler
	 	bit 7         0:      reserved in T1CON
 		bit 6         1:      TENABLE, 1 = enable timer
 		bit 5-4       00:     00 = CPUCLK is clock source
 		bit 3-2       10:     10 = reload immediately
 		bit 1         0:      0 = disable timer compare
 		bit 0         0:      reserved in T1CON
		*/
	}
	else
	{
		*T3CON = 0x0000;      /* disable timer 3 */
    	*GPTCONB = 0x0000;    /* configure GPTCONB */
	    *T3CNT = 0x0000;      /* clear timer counter */
	    *T3PR = period;       /* set timer period */
	    *DBTCONB = 0x0000;    /* deadband units off */
    
	    switch(channel)
    	{
    		case 7: 	*MCRC = *MCRC | 0x0002;
    					*ACTRB = *ACTRB & ~0x0003;
    					*ACTRB = *ACTRB | 0x0002;
    					*CMPR4 = 0;		/* set PWM7/8 duty cycle */
    					break;
    			
    		case 8: 	*MCRC = *MCRC | 0x0004;
    					*ACTRB = *ACTRB & ~0x000C;
    					*ACTRB = *ACTRB | 0x0008;
    					*CMPR4 = 0;
    					break;
    			
	    	case 9: 	*MCRC = *MCRC | 0x0008;
	    				*ACTRB = *ACTRB & ~0x0030;
    					*ACTRB = *ACTRB | 0x0020;
    					*CMPR5 = 0;     /* set PWM9/10 duty cycle */
    					break;
    			
	    	case 10: 	*MCRC = *MCRC | 0x0010;
    					*ACTRB = *ACTRB & ~0x00C0;
    					*ACTRB = *ACTRB | 0x0080;
    					*CMPR5 = 0;
    					break;
    			
	    	case 11: 	*MCRC = *MCRC | 0x0020;
    					*ACTRB = *ACTRB & ~0x0300;
    					*ACTRB = *ACTRB | 0x0200;
    					*CMPR6 = 0;     /* set PWM11/12 duty cycle */
    					break;
    			
	    	case 12: 	*MCRC = *MCRC | 0x0040;
    					*ACTRB = *ACTRB & ~0x0C00;
    					*ACTRB = *ACTRB | 0x0800;
    					*CMPR6 = 0;
    					break;
    }
     
    *COMCONB = 0x8200;    /* configure COMCONB register */
    *T3CON = 0xD048;      /* configure T3CON register */
	
	}
	return 0;
}

int setPWM(int channel, int dutycycle)
{   
	if ((channel < 1) || (channel > 12))
	{
		return -1;		/* returns -1 if channel is not valid */
	}
	
	if (channel < 7)    /* chooses between event managers */
	{
		switch(channel)
		{
			case 1:	*CMPR1 = dutycycle;
					break;
					
			case 2: *CMPR1 = dutycycle;
					break;
			
			case 3:	*CMPR2 = dutycycle;
					break;
					
			case 4: *CMPR2 = dutycycle;
					break;
					
			case 5:	*CMPR3 = dutycycle;
					break;
					
			case 6: *CMPR3 = dutycycle;
					break;
		}
	}
	else
	{
	    switch(channel)
		{
			case 7:		*CMPR4 = dutycycle;
						break;
					
			case 8: 	*CMPR4 = dutycycle;
						break;
			
			case 9:		*CMPR5 = dutycycle;
						break;
					
			case 10: 	*CMPR5 = dutycycle;
						break;
					
			case 11:	*CMPR6 = dutycycle;
						break;
					
			case 12: 	*CMPR6 = dutycycle;
						break;
		}
	}
	return 0;
}