?? rtl8019.h
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/*
This software is subject to the terms of the Inari HDK License
Agreement as indicated in the Inari HDK user's manual.
Copyright (C) 2001 Inari, Inc. All Rights Reserved.
You must accept the terms of that agreement to use this software.
Ethernet Router Ethernet Driver Header File.
*/
#ifndef _rtl8019_h
#define _rtl8019_h
#include "edt.h"
#include "Global.h" // Global Project defines
#define ROUTER_ETHCHIP_OVERRUN 'A'
#define ROUTER_ETHCHIP_BADREAD 'B'
#define ROUTER_ASSM_BAD 'C'
#define ROUTER_ASSM_LARGE 'D'
/* Ethernet Driver Generic Functions. */
extern void EthInit (void);
extern bit EthRecv (void);
extern WORD EthSend (EDT_RX_LIST* eth);
extern bit EthSendSetup(unsigned int ByteCount);
extern WORD EthSendCopy(unsigned int ByteCount, unsigned char* TxEthBuffer);
extern void EthSendFinish(unsigned int ByteCount);
extern BYTE* EthHeaderCheck(WORD, BYTE*);
extern void EthRxComplete(WORD, BYTE*);
/* RTL8019AS Driver Specific functions. */
void RTL_ISR(void);
BYTE CurrentPointer(void);
//Macro's
//to ease Byte mode in a Word world
#define MSB(Value) ((unsigned char)((((unsigned long)Value) >> 8) & 0xffL))
#define LSB(Value) ((unsigned char)(((unsigned long)Value) & 0xff))
#define SIZE_ETH_HEADER 0x000e //14 bytes for Ethernet header [Dest(6),Source(6),Type(2)]
#ifndef NULL
#define NULL 0x0000 //NullPointer?
#endif
#define _INSERT_WAIT_STATES //Add Wait States to Movx commands during DMAReads
//#define _INSERT_WAIT_STATES2 //Add more Wait States controls (ON & OFF)
#define CONTROL_BASE 0x0300
//
// Define Control Registers
//
typedef union _chipctrl //Lay all these structures on top of each other!!
{
struct _page0_rd
{ // RD / WR
unsigned char cr; // Command Register
unsigned char clda0; // Current Local DMA Address 0 / PSTART
unsigned char clda1; // Current Local DMA Address 1 / PSTOP
unsigned char bnry; // Boundary Pointer
unsigned char tsr; // Transmit Status Register / TPSR
unsigned char ncr; // Number of collisions / TBCR0
unsigned char fifo; // fifo
unsigned char isr; // Interrupt status register
unsigned char crda0; // Current Remote DMA Address0 / RSAR0
unsigned char crda1; // Current Remote DMA Address1 / RSAR1
unsigned char n8019id0; // Chip ID# 0x50='P' / RBCR0
unsigned char n8019id1; // Chip ID# 0x70='p' / RBCR1
unsigned char rsr; // Receive Status Register / RCR
unsigned char cntr0; // Frame Error counter / TCR
unsigned char cntr1; // CRC Error counter / DCR
unsigned char cntr2; // Missed Packet Error counter / IMR
} page0_rd;
struct _page0_wr
{ // WR
unsigned char cr; // Command Register
unsigned char pstart; // Page Start register
unsigned char pstop; // Page Stop register
unsigned char bnry; // Boundary Pointer
unsigned char tpsr; // Transmit Page Start Register
unsigned char tbcr0; // Transmit Byte Count Register0
unsigned char tbcr1; // Transmit Byte Count Register1
unsigned char isr; // Interrupt status register
unsigned char rsar0; // Remote Start Address Register0
unsigned char rsar1; // Remote Start Address Register1
unsigned char rbcr0; // Remote Byte Count Register0
unsigned char rbcr1; // Remote Byte Count Register1
unsigned char rcr; // Receive Configuration Register
unsigned char tcr; // Transmit Configuration Register
unsigned char dcr; // Data Configuration Register
unsigned char imr; // Interrupt Mask Register
} page0_wr;
struct _page1
{ // RD
unsigned char cr; // Command Register
unsigned char par0; // Physical Address Register0
unsigned char par1; // Physical Address Register1
unsigned char par2; // Physical Address Register2
unsigned char par3; // Physical Address Register3
unsigned char par4; // Physical Address Register4
unsigned char par5; // Physical Address Register5
unsigned char curr; // Current Page Register
unsigned char mar0; // Multicast Address Register0
unsigned char mar1; // Multicast Address Register1
unsigned char mar2; // Multicast Address Register2
unsigned char mar3; // Multicast Address Register3
unsigned char mar4; // Multicast Address Register4
unsigned char mar5; // Multicast Address Register5
unsigned char mar6; // Multicast Address Register6
unsigned char mar7; // Multicast Address Register7
} page1;
struct _page2_rd
{ // RD
unsigned char cr; // Command Register
unsigned char pstart; // Page Start Register
unsigned char pstop; // Page Stop Register
unsigned char p2_r3; // reserved
unsigned char tpsr; // Transmit Page Start Address
unsigned char p2_r5; // reserved
unsigned char p2_r6; // reserved
unsigned char p2_r7; // reserved
unsigned char p2_r8; // reserved
unsigned char p2_r9; // reserved
unsigned char p2_rA; // reserved
unsigned char p2_rB; // reserved
unsigned char rcr; // Receive Configuration Register
unsigned char tcr; // Transmit Configuration Register
unsigned char dcr; // Data Configuration Register
unsigned char imr; // Interrupt Mask Register
} page2_rd;
struct _page3_rd
{ // RD
unsigned char cr; // Command Register
unsigned char n9346cr; // 9346-EEProm Command Register
unsigned char bpage; // Boot ROM Page Register
unsigned char config0; // RTL8019AS Config Register0 // VersionID & Connector type
unsigned char config1; // RTL8019AS Config Register1 // IRQ Enable, IRQ Select Base Address Select
unsigned char config2; // RTL8019AS Config Register2 // Network Medium Select, BootRom Select
unsigned char config3; // RTL8019AS Config Register3 // PnP, FullDuplex, LEDS, Sleep, PowerDown
unsigned char p3_r7; // reserved
unsigned char csnsav; // CSN Save Register
unsigned char p3_r9; // reserved
unsigned char p3_rA; // reserved
unsigned char intr; // Interrupt register (reflects ISA bus Interrupt states)
unsigned char p3_rC; // reserved
unsigned char config4; // RTL8019AS Config Register4 // I/O Address Decode (IOMS)
unsigned char p3_rE; // reserved
unsigned char p3_rF; // reserved
} page3_rd;
struct _page3_wr
{ // WR
unsigned char cr; // Command Register
unsigned char n9346cr; // 9346-EEProm Command Register
unsigned char bpage; // Boot ROM Page Register
unsigned char p3_r3; //
unsigned char config1; // RTL8019AS Config Register1 // IRQ Enable, IRQ Select Base Address Select
unsigned char config2; // RTL8019AS Config Register2 // Network Medium Select, BootRom Select
unsigned char config3; // RTL8019AS Config Register3 // PnP, FullDuplex, LEDS, Sleep, PowerDown
unsigned char test; // Test
unsigned char p3_r8; // reserved
unsigned char hltclk; // Halt Clock Register
unsigned char p3_rA; // reserved
unsigned char p3_rB; // reserved
unsigned char fmwp; // Flash Memory Write Protect Register
unsigned char p3_rD; // reserved
unsigned char p3_rE; // reserved
unsigned char p3_rF; // reserved
} page3_wr;
} chipctrl;
//Defines for the different registers
//CR Bits
#define STP 0x01 // Stop Bit
#define STA 0x02 // Start Bit
#define TXP 0x04 // Transmit Packet bit
#define DMA_READ 0x08 // RD0 Read from Buffer to I/O
#define DMA_WRITE 0x10 // RD1 Write From I/O to Buffer
#define DMA_ABORT 0x20 // RD2 Abort/Complete any Read/Write activity
#define DMA_COMPLETE 0x20 // RD2 Abort/Complete any Read/Write activity
#define PAGE0 0x00 // PS0,1 = 00
#define PAGE1 0x40 // PS0,1 = 01
#define PAGE2 0x80 // PS0,1 = 10
#define PAGE3 0xC0 // PS0,1 = 11
//CR values
#define STOP_CHIP (DMA_ABORT | STP) //0x21
#define PAGE0_START (DMA_ABORT | STA) //0x22
#define USE_PAGE0 (PAGE0 | DMA_ABORT | STP) //0x21
#define USE_PAGE1 (PAGE1 | DMA_ABORT | STP) //0x61
#define USE_PAGE2 (PAGE2 | DMA_ABORT | STP) //0xA1
#define USE_PAGE3 (PAGE3 | DMA_ABORT | STP) //0xE1
#define TX_PACKET (DMA_COMPLETE | TXP) //0x24
#define SEND_PACKET (DMA_WRITE | DMA_READ| STA) // RD0,1 = 11 AutoSetup Read from ChipBuffer
#define WRITE_MEM (DMA_WRITE | STA) //
#define READ_MEM (DMA_READ | STA) //
// ISR values
#define PRX 0x01 // Packet Received -No Errors
#define PTX 0x02 // Packet Transmitted -No Errors
#define RXE 0x04 // Packet Received With Errors
#define TXE 0x08 // Packet Transmit Aborted -With Errors (Excessive Collisions)
#define OVW 0x10 // Receive Buffer Overwrite Error
#define CNT 0x20 // MSB of (one or more) Error Counters is SET
#define RDC 0x40 // Remote DMA operation complete
#define RST 0x80 // NIC has entered reset mode
// IMR values
#define PRXE 0x01 // Packet Received Enable
#define PTXE 0x02 // Packet Transmitted Enable
#define RXEE 0x04 // Packet Received With Errors Enable
#define TXEE 0x08 // Packet Transmit Error Enable
#define OVWE 0x10 // Receive Buffer Overwrite Error
#define CNTE 0x20 // MSB of (one or more) Error Counters is SET
#define RDCE 0x40 // Remote DMA operation complete
//#define INTERRUPT_MASK (PRXE | PTXE | TXEE) //enable these interrupts
#define INTERRUPT_MASK (PRXE | PTXE | RXEE | TXEE) //enable these interrupts
//#define INTERRUPT_MASK (PRXE | PTXE | RXEE | TXEE | OVWE | CNTE | RDCE) //enable these interrupts
//DCR values
#define WTS 0x01 // WordTransferSelect
//#define PTX 0x02 // ByteOrder 1=BigIndian
#define LAS 0x04 // LongAddressSelect (Not Supported!)
#define LS 0x08 // Loopback Select
#define ARM 0x10 // Auto-initialize Remote DMA
#define FT0 0x20 // Fifo Threshold0 /00=2bytes, 01=4bytes
#define FT1 0x40 // Fifo Threshold1 /10=8bytes, 11=12bytes
#define dcr_reserved 0x80 //
#define FIFO_THRESHOLD (FT0 | FT1 | ARM) // Fifo Threshold = 8 bytes, SendPacket command used)
//Buffer Size defines
#define TX0_PAGE_START 0x40 // Start at the beginning of 8KRam at 0x4000
//#define TX1_PAGE_START 0x46 // Start after 1st TxBuffer 0x4600
//#define RECEIVE_PAGE_START 0x4C // Start after all TxBuffers 0x4C00
#define RECEIVE_PAGE_START 0x46 // Start after all TxBuffers 0x4600
#define RECEIVE_PAGE_STOP 0x60 // Circle at the end of 8KRam at 0x5FFF
//RCR values
#define RCR_ACCEPT_ERR 0x01 // accept error packets
#define RCR_ACCEPT_SMALL 0x02 // accept short(<64) packets
#define RCR_BROADCAST 0x04 // receive broadcast packets
#define RCR_MULTICAST 0x08 // receive multicast packets
#define RCR_ALL_PHYS 0x10 // receive ALL directed packets
#define RCR_MONITOR 0x20 // don't collect packets
#define RECEIVE_ANYTHING (RCR_BROADCAST | RCR_ALL_PHYS | RCR_MULTICAST | RCR_ACCEPT_SMALL | RCR_ACCEPT_ERR)
#define RECEIVE_ALL (RCR_BROADCAST | RCR_ALL_PHYS | RCR_MULTICAST)
#define RECEIVE_MULTI (RCR_BROADCAST | RCR_MULTICAST)
#define RECEIVE_ADDRESS (RCR_BROADCAST)
//TCR Values
#define CRC_DISABLE 0x01
#define LB0 0x02 // Loopback Internal
#define LB1 0x04 // Loopback External
#define ATD 0x08 // Auto Transmit Disable
#define OFST 0x10 // Collision Offset Enable
#define NORMAL_TRANSMIT 0x00 // CRC Enabled, Not in Loopback, AT enabled & no Collision offset
#define INTERNAL_LOOPBACK LB0 // Internal Loopback mode 1
#define EXTERNAL_LOOPBACK2 LB1 // External Loopback mode 2
#define EXTERNAL_LOOPBACK3 (LB1 | LB0) // External Loopback mode 3
#endif // _rtl8019_h
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