--divider.vhd n-bit divider
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all ;
use work.components.all ;
entity divider is
generic ( n : integer := 7 ) ;
port (
  clock	: in std_logic ;--clock
  s : in std_logic ;--start operation
  la : in std_logic ;--load of dividend
  eb: in std_logic ;--enable(load) of divisor
  dataa	: in std_logic_vector(n-1 downto 0) ;--dividend
  datab	: in std_logic_vector(n-1 downto 0) ;--divisor
  r : buffer std_logic_vector(n-1 downto 0) ;--remainder
  q : buffer std_logic_vector(n-1 downto 0) ;--quotient
  done : out std_logic ) ;--done operation
end divider ;
architecture behavior of divider is
  type state_type is ( s1, s2, s3 ) ;--state declaration
  signal y : state_type ;--state definition
  signal zero : std_logic ;--one bit zero
  signal cout : std_logic ;--subtractor carry-out
  signal z : std_logic ;--detecter of zero
  signal ea : std_logic ;--enable of dividend
  signal rsel : std_logic ;--selected line of register r's multiplexer
  signal lr : std_logic ;--load of quotient
  signal er : std_logic ;--enable of quotient
  signal er0: std_logic ;--enable of rr0 register
  signal lc : std_logic ;--load of downcounter
  signal ec : std_logic ;--enable of downcounter
  signal r0 : std_logic ;--output of register a's multiplexer
  signal a : std_logic_vector(n-1 downto 0) ;--output of register a(dividend)
  signal b : std_logic_vector(n-1 downto 0) ;--output of register b(divisor)
  signal datar : std_logic_vector(n-1 downto 0) ;--parallel load of register r(remainder)
  signal sum : std_logic_vector(n downto 0) ;--sum of subtractor
  signal count : integer range 0 to n-1 ;--range of downcounter	
begin
  fsm_transitions: process ( clock )
  begin
 	if (clock'event and clock = '1') then
	  case y is
	  when s1 =>
		if s = '0' then	y <= s1 ; else y <= s2 ; end if ;
	  when s2 =>
		if z = '0' then y <= s2 ; else y <= s3 ; end if ;
	  when s3 =>
		if s = '1' then y <= s3 ; else y <= s1 ; end if ;
	  end case ;
	end if ;
  end process ;
  fsm_outputs: process ( s, y, cout, z )
  begin
	lr <= '0' ; er <= '0' ; er0 <= '0' ;--initialize value			
	ea <= '0' ; done <= '0' ;	
	rsel <= '0' ;						
	case y is
	  when s1 =>						
	 	er <= '1' ;	
	    if s = '0' then						
		  lr <= '1' ; 			
		  if la = '1' then ea <= '1' ; else ea <= '0' ; end if ;	
		else
		  ea <= '1' ; er0 <= '1' ; 	
		end if ;
	  when s2 =>
		rsel <= '1' ; er <= '1' ; er0 <= '1' ; ea <= '1' ;	
		if cout = '1' then lr <= '1' ; else	lr <= '0' ; end if ;
	  when s3 =>
		done <= '1' ;
	end case ;
  end process ;
  -- define the datapath circuit
  zero <= '0' ;
  --divisor
  regb: regne generic map ( n => n )
	port map ( datab, eb, clock, b ) ;		
  --remainder
  shiftr: shiftlne generic map ( n => n )				
	port map ( datar, lr, er, r0, clock, r ) ;		
  --flip-flop with multiplexer
  ff_r0: muxdff port map ( zero, a(n-1), er0, clock, r0 ) ;	

  --dividend
  shifta: shiftlne generic map ( n => n )				
	port map ( dataa, la, ea, cout, clock, a ) ;
  q <= a ;
  --downcounter
  ec <= '1' ; lc <= not s;
  counter: downcnt generic map ( modulus => n+1 ) 
	port map ( clock, ec, lc, count ) ;
  --nor gate zero detector 
  z <= '1' when count = 0 else '0' ;
  --subtractor
  sum <= r & r0 + (not b +1) ;
  cout <= sum(n) ;
  --multiplexer of register r(remainder) 
  datar <= (others => '0') when rsel = '0' else sum(n-1 downto 0) ;
end behavior ;