/* romInit.s - Zhongxing 860fuc ROM initialization module *//* Copyright 1984-1996 Wind River Systems, Inc. */	.data	.globl  copyright_wind_river	.long   copyright_wind_river/*modification history--------------------01m,26jan99,cn   added support for SDRAM (SPR# 24337). Also removed checks 		 to BCSR2_DRAM_NO_EDO_L and BCSR2_DRAM_EDO_L as this bit 		 is not actually implemented.  01l,09nov98,cn   added support for FADS860T boards.01k,30jul98,gls  fixed to initialize CS0/CS1 earlier to allow access to BCSR301j,18feb98,gls	 added support for PPC823FADS01i,23jun97,map  fixed MAMR init for 16/32 DRAM [SPR# 8753]01h,17dec96,tpr  fixed MAMR init. bug with 16 and 32 Mbytes dram (SPR #7661)01g,10nov96,tpr  updated UPM table. 		 removed RTCSC initialization.01f,08nov96,tpr  modified UPM table for EDO Dram @ 50 Mhz.01e,06nov96,tpr  replaced PLPRCR_MF_SFT by PLPRCR_MF_SHIFT.01d,06nov96,tpr  Clean up the code (SPR #7336).		 added DRAM speed selection (SPR #7335).01c,24jun96,tpr  Reworked all initialization code.01b,04jun96,cah  Add mem controller minimal init sequence01a,19apr96,tpr  written.*//*DESCRIPTIONThis module contains the entry code for the VxWorks bootrom.The entry point romInit, is the first code executed on power-up.It sets the BOOT_COLD parameter to be passed to the genericromStart() routine.The routine sysToMonitor() jumps to the location 4 bytespast the beginning of romInit, to perform a "warm boot".This entry point allows a parameter to be passed to romStart().*/#define	_ASMLANGUAGE#include "vxWorks.h"#include "asm.h"#include "cacheLib.h"#include "config.h"#include "regs.h"	#include "sysLib.h"#include "drv/multi/ppc860Siu.h"#include "ads860.h"	#define MAMR_DEFAULT_VALUE ( MAMR_AMA_TYPE_0 | 		\			    MAMR_DSA_4_CYCL | MAMR_G0CLA_A11 | 		\			    MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X) #define MBMR_DEFAULT_VALUE (MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | 	\			    MAMR_G0CLA_A11 | MAMR_RLFA_1X | 		\			    MAMR_WLFA_1X | MAMR_TLFA_1X)	/* internals */	.globl	_romInit	/* start of system code */	.globl	romInit		/* start of system code */		/* externals */	.extern romStart	/* system initialization routine */	.extern cStartup   	.extern HdwInitDRAM	.text	.align 2/******************************************************************************** romInit - entry point for VxWorks in ROM** romInit*     (*     int startType	/@ only used by 2nd entry point @/*     )*/_romInit:romInit:	bl	cold		/* jump to the cold boot initialization */		bl	start		/* jump to the warm boot initialization */	/* copyright notice appears at beginning of ROM (in TEXT segment) */	.ascii   "Copyright 1984-1996 Wind River Systems, Inc."	.align 2cold:	li	r3, BOOT_COLD	/* set cold boot as start type */	/*	 * When the PowerPC 860 is powered on, the processor fletch the	 * instructions located at the address 0x100. We need to jump	 * from the address 0x100 to the Flash space.	 */	lis	r4, HIADJ(start)		/* load r4 with the address */	addi	r4, r4, LO(start)		/* of start */	lis	r5, HIADJ(romInit)		/* load r5 with the address */	addi	r5, r5, LO(romInit)		/* of romInit() */	lis	r6, HIADJ(ROM_TEXT_ADRS)	/* load r6 with the address */	addi	r6, r6, LO(ROM_TEXT_ADRS)	/* of ROM_TEXT_ADRS */	sub	r4, r4, r5			/*  */	add	r4, r4, r6 	mtspr	LR, r4				/* save destination address*/						/* into LR register */	blr					/* jump to flash mem address */			start:	/* set the MSR register to a known state */			xor	r4, r4, r4		/* clear register R4 */	mtmsr 	r4			/* cleat the MSR register */	/* DER - clear the Debug Enable Register */	mtspr	DER, r4	/* ICR - clear the Interrupt Cause Register */	mtspr	ICR, r4	/* 	 * ICTRL - initialize the Intstruction Support Control register	 *	   	 */	lis	r5, HIADJ(0x00000007)	addi	r5, r5, LO(0x00000007)	mtspr	ICTRL, r5	/* disable the instruction/data cache */		lis	r4, HIADJ ( CACHE_CMD_DISABLE)		/* load disable cmd */	addi	r4, r4, LO (CACHE_CMD_DISABLE)	mtspr	IC_CST, r4				/* disable I cache */	mtspr	DC_CST, r4				/* disable D cache */	/* unlock the instruction/data cache */	lis	r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)	/* load unlock cmd */	addi	r4, r4, LO (CACHE_CMD_UNLOCK_ALL)	mtspr	IC_CST, r4			/* unlock all I cache lines */	mtspr	DC_CST, r4			/* unlock all D cache lines */	/* invalidate the instruction/data cache */	lis	r4, HIADJ (CACHE_CMD_INVALIDATE)   /* load invalidate cmd*/	addi	r4, r4, LO (CACHE_CMD_INVALIDATE)	mtspr	IC_CST, r4		/* invalidate all I cache lines */	mtspr	DC_CST, r4		/* invalidate all D cache lines */	/*	 * initialize the IMMR register before any non-core registers	 * modification.	 */	lis	r4, HIADJ( INTERNAL_MEM_MAP_ADDR)		addi	r4, r4, LO(INTERNAL_MEM_MAP_ADDR)	mtspr	IMMR, r4		/* initialize the IMMR register */	mfspr	r4, IMMR		/* read it back, to be sure */	rlwinm  r4, r4, 0, 0, 15	/* only high 16 bits count */			/* SYPCR - turn off the system protection stuff */			lis	r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)	addi	r5, r5, LO(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)	stw	r5, SYPCR(0)(r4)	/*	 * Map the bank 0 to the flash area - On the ADS board at reset time	 * the bank 0 is already used to map the flash.	 */	lis r5, HIADJ(0xfff00501)	addi r5, r5,LO(0xfff00501)	stw r5,BR0(0)(r4)	lis r5, HIADJ(0xfff80926)	addi r5,r5,LO(0xfff80926)	stw r5,OR0(0)(r4)	/*add by hubing begin*/	/* Map the bank 1 FLASH 16m-2000000 */	lis	r5, HIADJ(0xff000000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | \			   OR_TRLX)	addi	r5, r5, LO(0xff000000 | OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | \			   OR_TRLX)	stw	r5, OR1(0)(r4)		lis	r5, HIADJ((FLASH_BASE_ADRS & BR_BA_MSK) | BR_V | BR_PS_16)	addi	r5, r5, LO((FLASH_BASE_ADRS & BR_BA_MSK) | BR_V | BR_PS_16)	stw	r5, BR1(0)(r4)	lis	r6, HIADJ(0x600040)	addi	r6, r6, LO( 0x600040)	siu_done:			/*modi by xdy begin*/	lwz	r5, SIUMCR(0)(r4)	or	r5, r5, r6	stw	r5, SIUMCR(0)(r4)	/* TBSCR - initialize the Time Base Status and Control register */	lis	r5, HIADJ( TBSCR_REFA | TBSCR_REFB)	addi	r5, r5, LO(TBSCR_REFA | TBSCR_REFB)	sth	r5, TBSCR(0)(r4)	/* set PIT status and control init value */	li	r5, PISCR_PS | PISCR_PITF	sth	r5, PISCR(0)(r4)	/* set the SPLL frequency */	lis	r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \								PLPRCR_TEXPS)	addi	r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \								PLPRCR_TEXPS)	stw	r5, PLPRCR(0)(r4)	/* 	 * we program the MPTPR with the largest allowed divider 	 * and the PTA value accordingly. So here we figure out the 	 * correct value for the PTA field.	 */	li	r6, MPTPR_PTP_DIV64         lis     r11, HIADJ ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 64) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 32 */	li	r6, MPTPR_PTP_DIV32         lis     r11, HIADJ ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 32) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 16 */	li	r6, MPTPR_PTP_DIV16         lis     r11, HIADJ ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 16) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 8 */	li	r6, MPTPR_PTP_DIV8         lis     r11, HIADJ ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 8) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* try with the divider by 4 */	li	r6, MPTPR_PTP_DIV4         lis     r11, HIADJ ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 4) << MAMR_PTA_SHIFT)        cmpwi   r11,0        bne     mptprInit	/* it has to be the divide by 2 */	li	r6, MPTPR_PTP_DIV2         lis     r11, HIADJ ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)        addi    r11, r11, LO ((REFRESH_VALUE / 2) << MAMR_PTA_SHIFT)	/*modi by xdy end*/mptprInit:	/* program the MPTPR */	sth	r6, MPTPR(0)(r4)         /* 	 * initialize MxMR but don't enable refresh until after 	 * SDRAM initialization.         */        lis     r6, HIADJ (MAMR_DEFAULT_VALUE)        addi    r6, r6, LO (MAMR_DEFAULT_VALUE)        or      r6, r6, r11                              stw     r6, MAMR(0)(r4)        lis     r6, HIADJ (MBMR_DEFAULT_VALUE)        addi    r6, r6, LO (MBMR_DEFAULT_VALUE)        or      r6, r6, r11                             stw     r6, MBMR(0)(r4)upmaInit:        /*         * load r6/r7 with the start/end address of the UPM table for an         * SDRAM @ 50MHZ.         */        lis     r6, HIADJ( upmTableSdram)        addi    r6, r6, LO(upmTableSdram)        lis     r7, HIADJ( upmTableSdramEnd)        addi    r7, r7, LO(upmTableSdramEnd)         /* init UPMB for memory access */         sub     r5, r7, r6              /* compute table size */        srawi   r5, r5, 2               /* in integer size */         /* convert UpmTable to ROM based addressing */         lis     r7, HIADJ(romInit)        addi    r7, r7, LO(romInit)         lis     r8, HIADJ(ROM_TEXT_ADRS)        addi    r8, r8, LO(ROM_TEXT_ADRS)         sub     r6, r6, r7              /* subtract romInit base address */        add     r6, r6, r8              /* add in ROM_TEXT_ADRS address */ /*mody from cs0 to cs2 hubing*/        lis     r9, HIADJ (MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS2)        addi    r9, r9, LO(MCR_OP_WRITE | MCR_UM_UPMA | MCR_MB_CS2) UpmWriteLoop:        /* write the UPM table in the UPM */         lwz     r10, 0(r6)              /* get data from table */        stw     r10, MDR(0)(r4)         /* store the data to MD register */         stw     r9, MCR(0)(r4)          /* issue command to MCR register */         addi    r6, r6, 4               /* next entry in the table */        addi    r9, r9, 1               /* next MAD address */        addi    r5,r5,-1        cmpwi   r5,0        bne     UpmWriteLoop        /*          * Issue precharge command (PRCG) and wait the precharge time (t-rp).	 * Run precharge pattern from UPMA location 5.         */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			  MCR_MCLF_1X | 0x5)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			   MCR_MCLF_1X | 0x5)        stw     r5, MCR(0)(r4)         /* run refresh pattern 8 times */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			  MCR_MCLF_8X | 0x30)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			  MCR_MCLF_8X | 0x30)        stw     r5, MCR(0)(r4)         /* 	 * Configure the 32 bit address to be output on the address bus 	 * if AMX = 0xb11.         * See section 16.6.4.1 "Arm Words".  The following values must 	 * be placed on the defined SDRAM address pins:         *   A[9]   = 0          burst write mode         *   A[6:4] = 010        cas latency of two         *   A[3]   = 0          sequential mode         *   A[2:0] = 010        burst length 4         *         * The address must be shifted left by 2 bits for 32 bit wide SDRAM...         *   (0b0100010 << 2) = 0x88         */        lis     r5, HIADJ(LOCAL_MEM_LOCAL_ADRS | 0x88)        addi    r5, r5, LO(LOCAL_MEM_LOCAL_ADRS | 0x88)        stw     r5, MAR(0)(r4)         /* 	 * issue a mode register set (MRS) to initialize the SDRAM mode 	 * register.  This programs the burst length, CAS latency and 	 * write mode. Run MRS pattern from UPMB location 6.         */        lis     r5, HIADJ(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			  MCR_MCLF_1X | 0x6)        addi    r5, r5, LO(MCR_OP_RUN | MCR_UM_UPMA | MCR_MB_CS2 | \			  MCR_MCLF_1X | 0x6)        stw     r5, MCR(0)(r4)	/* program OR2 and BR2 for 4 Mbytes SDRAM Memory Array */	lis	r5, HIADJ  ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)	addi    r5, r5, LO ((~(SDRAM_SIZE - 1)) | OR_CSNT_SAM)	stw	r5, OR2(0)(r4)	/* set OR2 to the previously computed value */	lis	r5, HIADJ ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA \			    | BR_V)	addi    r5, r5, LO ((LOCAL_MEM_LOCAL_ADRS & BR_BA_MSK) | BR_MS_UPMA \			    | BR_V)	stw	r5, BR2(0)(r4)	/* enable SDRAM refresh cycles */        lis     r5, HIADJ (MAMR_DEFAULT_VALUE | MAMR_PTBE)        addi    r5, r5,LO (MAMR_DEFAULT_VALUE | MAMR_PTBE)	add	r5, r5, r11        stw     r5, MAMR(0)(r4)  	/* initialize the stack pointer */	lis	sp, HIADJ(STACK_ADRS)	addi	sp, sp, LO(STACK_ADRS)	        /* initialize r2 and r13 according to EABI standard */	/* go to C entry point */	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */	/* 	 * calculate C entry point: routine - entry point + ROM base 	 * routine	= romStart	 * entry point	= romInit	= R7	 * ROM base	= ROM_TEXT_ADRS = R8	 * C entry point: romStart - R7 + R8 	 */        lis	r6, HIADJ(romStart)	        addi	r6, r6, LO(romStart)	/* load R6 with C entry point */	sub	r6, r6, r7		/* routine - entry point */	add	r6, r6, r8 		/* + ROM base */	mtlr	r6			/* move C entry point to LR */	blr				/* jump to the C entry point *//* This 50 MHz SDRAM table is for... *   860EN Rev B.1 9829 and newer silicon *   860T  Rev B.3 9832 and newer silicon * * This table will NOT work with older 860EN or 860T parts. */ upmTableSdram: /* single read   (offset 0x00 in upm ram) */       .long   0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00       .long   0x1ff77c47, 0x1ff77c35, 0xefeabc34, 0x1fb57c35/* burst read    (offset 0x08 in upm ram) */       .long   0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00       .long   0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* single write  (offset 0x18 in upm ram) */       .long   0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* burst write   (offset 0x20 in upm ram) */       .long   0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00       .long   0xf0affc00, 0xe1bbbc04, 0x1ff77c47, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* refresh       (offset 0x30 in upm ram) */       .long   0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04       .long   0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04       .long   0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04/* exception     (offset 0x3C in upm ram) */       .long   0x7ffffc07, 0xfffffc04, 0xfffffc04, 0xfffffc04 upmTableSdramEnd: