/* ; ------------------------------------------------------------------; Header: bsp.h - Fujitsu 832EK eval. board low level routines.;; uC/OS Real-time multitasking kernel for the Fujitsu SPARClite processor.;; Written by Brad Denniston (bradd@vpeng.com) Sept 1998; Description: ;	Board support package for Fujitsu SPARClite EV832 evaluation board.;	Defines for timer ; ------------------------------------------------------------------*/#ifndef _BSP_H_#define _BSP_H_/* SIO channels: /* Interrupts on this board */#define	TMR1_RELOAD		0x4e1f0000	/* Timer1 reload value */#define	TRIGGER_MODE1	0x05100000#define	IRL_CLEAR		0x00100000#define	TRIGGER_MODE0	0x11c00000	/* int 11 falling edge */#define	IRQ_MASK		0xf7fe0000	/* int 11 -- 1 second timer */#define	IRQ_ALLMASK		0xffff0000	/* mask all ints */#define	IRL_ALLCLEAR	0xffff0000	/* clear all ints *//* timers - there are 3 counters in the 82C54 timer chip */# define TIMER_BASE_ADDR	0x14000003# define TREGCTL	0xc				/* control register */# define TREG0		0x0				/* counter 0 */# define TREG1		0x4				/* counter 1 */# define TREG2		0x8				/* counter 2 */# define TIMER_VAL0	10# define TIMER_VAL1	50# define TIMER_VAL2	500# define TIMER_SEC_RELOAD 20000		/* 1 second */# define TIMER_TASK_TIME	1000	/* 20 ticks/sec *//* counter control word is formatted as: 	SC  SC  RW  RW  MO  MO  MO  BCD *//* SC bits select a counter control word or readback */# define CTR_SELECT0	(0<<6)# define CTR_SELECT1	(1<<6)# define CTR_SELECT2	(2<<6)# define CTR_READBACK	(3<<6)/* Read/Write bits */# define CTR_RWLATCH	(0<<4)	/* latch the counter */# define CTR_RWLOW	(1<<4)		/* read only low byte */# define CTR_RWHIGH	(2<<4)		/* read only high byte */# define CTR_RWLOHI	(3<<4)		/* read low, then high byte */# define CTR_16BIT	0			/* set counter to 16-bit vs. bcd *//* counter mode */# define CTR_MODE0	(0<<1)		/* interrupt on terminal count, must reload */# define CTR_MODE1	(1<<1)		/* hardware retriggerable one-shot */# define CTR_MODE2	(2<<1)		/* rate generator for real time clock */# define CTR_MODE3	(3<<1)		/* square wave - baud rate generation */# define CTR_MODE4	(4<<1)		/* pulse when count reaches 0 */# define CTR_MODE5	(5<<1)		/* hardware triggered strobe *//* address space */#define CC1_ASI		4#define IRC_ASI		7#define IRC_BASE	0x00000000#ifdef LANGUAGE_Cvoid InitTimer();void BSPInit();#endif#endif    /* _BSP_H_ */