RF:16:IN:0:REG:8 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
    RF:17:IN:0:REG:8 = B:28 STAGE:-1 VAR: cluster#id DATATYPE: ANYINT,
    B:42 = RF:18:OUT:5:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U2:IN:2 = B:42 VAR: hw_const#0 DATATYPE: ANYINT,
    B:16 = RF:5:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U2:IN:0 = B:16 VAR: hw_const#0 DATATYPE: ANYINT,
    B:31 = U2:OUT:0 INSTR_LOG:1|tmp#13#||0 VAR: tmp#13 DATATYPE: UINT,
    RF:6:IN:0:REG:1 = B:31 STAGE:-1 VAR: tmp#13 DATATYPE: UINT,
    B:9 = RF:15:OUT:0:REG:0 VAR: hw_const#8 DATATYPE: ANYINT,
    U7:IN:1 = B:9 VAR: hw_const#8 DATATYPE: ANYINT,
    B:8 = RF:2:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U7:IN:0 = B:8 VAR: hw_const#0 DATATYPE: ANYINT,
    B:27 = U7:OUT:0 INSTR_LOG:1|b32_to_lo#||0 VAR: b32_to_lo DATATYPE: BYTE4,
    RF:12:IN:0:REG:8 = B:27 STAGE:-1 VAR: b32_to_lo DATATYPE: BYTE4,
    RF:13:IN:0:REG:8 = B:27 STAGE:-1 VAR: b32_to_lo DATATYPE: BYTE4,
    B:40 = RF:18:OUT:3:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U0:IN:2 = B:40 VAR: hw_const#0 DATATYPE: ANYINT,
    B:12 = RF:3:OUT:0:REG:1 VAR: pframe DATATYPE: CC,
    U0:IN:0 = B:12 VAR: pframe DATATYPE: CC,
    B:45 = U0:OUT:0 INSTR_LOG:1|pframe#||0 VAR: pframe DATATYPE: CC,
    RF:18:IN:0:REG:1 = B:45 STAGE:-1 VAR: pframe DATATYPE: CC,
    //  IN:DIVIDER_0: ( cluster#id ) = SELECT( hw_const#0 == CCRF_0[0], cluster#id == UNITRF_CID_0[0] )
    // OUT:DIVIDER_0: SELECT => ( cluster#id == SPIDXRF_0[8], cluster#id == SPIDXRF_1[8] )
    //  IN:ADDER_2: ( tmp#13 ) = NSELECT( hw_const#0 == CCRF_0[0], hw_const#0 == UNITRF_0_4[0] )
    // OUT:ADDER_2: NSELECT => ( tmp#13 == UNITRF_1_0[1] )
    //  IN:COMM_SCHED_0: ( b32_to_lo ) = COMMUCDATA( hw_const#8 == PERMRF_0[0], hw_const#0 == UNITRF_0_1[0], uc_const#0x88888823 == UCRF_0[9] )
    // OUT:COMM_SCHED_0: COMMUCDATA => ( b32_to_lo == MULRF_1_0[8], b32_to_lo == MULRF_1_1[8] )
    //  IN:ADDER_0: ( pframe ) = NSELECT( hw_const#0 == CCRF_0[0], pframe == UNITRF_0_2[1] )
    // OUT:ADDER_0: NSELECT => ( pframe == CCRF_0[1] )
    DEAD_REGS: {  };
instr: 25
    MC: OP: NONE LINE:-1 UCRF_RD:5,
    U6: OP: SPWRITE LINE:136 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:136
    U7: OP: COMMUCPERM LINE:137 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:137
    U6: OP: SPREAD_WT LINE:139 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:139
    B:7 = RF:17:OUT:0:REG:5 VAR: idx5 DATATYPE: INT,
    U6:IN:2 = B:7 VAR: idx5 DATATYPE: INT,
    B:6 = RF:1:OUT:0:REG:7 VAR: tmp#46 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#46 DATATYPE: UNDEFINED,
    B:8 = RF:2:OUT:0:REG:1 VAR: tmp#47 DATATYPE: HALF2,
    U7:IN:0 = B:8 VAR: tmp#47 DATATYPE: HALF2,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#48#||0 VAR: tmp#48 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:7 = B:27 STAGE:1 VAR: tmp#48 DATATYPE: UNDEFINED,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#49#||0 VAR: tmp#49 DATATYPE: HALF2,
    RF:2:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#49 DATATYPE: HALF2,
    B:5 = RF:16:OUT:0:REG:6 VAR: idx6 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx6 DATATYPE: INT,
    //  IN:SP_SCHED_WRITE_0: ( diffy ) = SPWRITE( idx5 == SPIDXRF_1[5], tmp#46 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    //  IN:COMM_SCHED_0: ( tmp#48 ) = COMMUCPERM( perm_d == UCRF_0[5], tmp#47 == UNITRF_0_1[1] )
    // OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#48 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#49 == UNITRF_0_1[1] )
    //  IN:SP_SCHED_READ_0: ( tmp#51 ) = SPREAD_WT( idx6 == SPIDXRF_0[6], diffy21 == SP_SCHED_RF_0[8] )
    DEAD_REGS: {  };
instr: 26
    MC: OP: NONE LINE:-1 UCRF_RD:6,
    U6: OP: SPWRITE LINE:137 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:137
    U7: OP: COMMUCPERM LINE:138 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:138
    U6: OP: SPREAD_WT LINE:140 SP_BASE:8 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:140
    B:7 = RF:17:OUT:0:REG:4 VAR: idx4 DATATYPE: INT,
    U6:IN:2 = B:7 VAR: idx4 DATATYPE: INT,
    B:6 = RF:1:OUT:0:REG:7 VAR: tmp#48 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#48 DATATYPE: UNDEFINED,
    B:8 = RF:2:OUT:0:REG:1 VAR: tmp#49 DATATYPE: HALF2,
    U7:IN:0 = B:8 VAR: tmp#49 DATATYPE: HALF2,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#50#||0 VAR: tmp#50 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:7 = B:27 STAGE:1 VAR: tmp#50 DATATYPE: UNDEFINED,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#51#||0 VAR: tmp#51 DATATYPE: HALF2,
    RF:2:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#51 DATATYPE: HALF2,
    B:5 = RF:16:OUT:0:REG:7 VAR: idx7 DATATYPE: INT,
    U6:IN:0 = B:5 VAR: idx7 DATATYPE: INT,
    //  IN:SP_SCHED_WRITE_0: ( diffy ) = SPWRITE( idx4 == SPIDXRF_1[4], tmp#48 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    //  IN:COMM_SCHED_0: ( tmp#50 ) = COMMUCPERM( perm_e == UCRF_0[6], tmp#49 == UNITRF_0_1[1] )
    // OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#50 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#51 == UNITRF_0_1[1] )
    //  IN:SP_SCHED_READ_0: ( tmp#53 ) = SPREAD_WT( idx7 == SPIDXRF_0[7], diffy21 == SP_SCHED_RF_0[8] )
    DEAD_REGS: {  };
instr: 27
    MC: OP: NONE LINE:-1 UCRF_RD:7,
    U6: OP: SPWRITE LINE:138 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:138
    U7: OP: COMMUCPERM LINE:139 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:139
    B:7 = RF:17:OUT:0:REG:3 VAR: idx3 DATATYPE: INT,
    U6:IN:2 = B:7 VAR: idx3 DATATYPE: INT,
    B:6 = RF:1:OUT:0:REG:7 VAR: tmp#50 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#50 DATATYPE: UNDEFINED,
    B:8 = RF:2:OUT:0:REG:1 VAR: tmp#51 DATATYPE: HALF2,
    U7:IN:0 = B:8 VAR: tmp#51 DATATYPE: HALF2,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#52#||0 VAR: tmp#52 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:7 = B:27 STAGE:1 VAR: tmp#52 DATATYPE: UNDEFINED,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#53#||0 VAR: tmp#53 DATATYPE: HALF2,
    RF:2:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#53 DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( diffy ) = SPWRITE( idx3 == SPIDXRF_1[3], tmp#50 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    //  IN:COMM_SCHED_0: ( tmp#52 ) = COMMUCPERM( perm_f == UCRF_0[7], tmp#51 == UNITRF_0_1[1] )
    // OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#52 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#53 == UNITRF_0_1[1] )
    DEAD_REGS: {  };
instr: 28
    MC: OP: NONE LINE:-1 UCRF_RD:8,
    U6: OP: SPWRITE LINE:139 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:139
    U7: OP: COMMUCPERM LINE:140 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:140
    B:7 = RF:17:OUT:0:REG:2 VAR: idx2 DATATYPE: INT,
    U6:IN:2 = B:7 VAR: idx2 DATATYPE: INT,
    B:6 = RF:1:OUT:0:REG:7 VAR: tmp#52 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#52 DATATYPE: UNDEFINED,
    B:8 = RF:2:OUT:0:REG:1 VAR: tmp#53 DATATYPE: HALF2,
    U7:IN:0 = B:8 VAR: tmp#53 DATATYPE: HALF2,
    B:27 = U7:OUT:0 INSTR_LOG:1|tmp#54#||0 VAR: tmp#54 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:7 = B:27 STAGE:1 VAR: tmp#54 DATATYPE: UNDEFINED,
    //  IN:SP_SCHED_WRITE_0: ( diffy ) = SPWRITE( idx2 == SPIDXRF_1[2], tmp#52 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    //  IN:COMM_SCHED_0: ( tmp#54 ) = COMMUCPERM( perm_g == UCRF_0[8], tmp#53 == UNITRF_0_1[1] )
    // OUT:COMM_SCHED_0: COMMUCPERM => ( tmp#54 == UNITRF_0_0[7] )
    DEAD_REGS: {  };
instr: 29
    MC: OP: NONE LINE:-1,
    U6: OP: SPREAD_WT LINE:168 SP_BASE:4 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:168
    U6: OP: SPWRITE LINE:140 SP_BASE:0 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:140
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:7 = RF:17:OUT:0:REG:1 VAR: idx1 DATATYPE: INT,
    U6:IN:2 = B:7 VAR: idx1 DATATYPE: INT,
    B:6 = RF:1:OUT:0:REG:7 VAR: tmp#54 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#54 DATATYPE: UNDEFINED,
    //  IN:SP_SCHED_READ_0: ( tmp#72 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], diffy == SP_SCHED_RF_0[0] )
    //  IN:SP_SCHED_WRITE_0: ( diffy ) = SPWRITE( idx1 == SPIDXRF_1[1], tmp#54 == UNITRF_0_0[7] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    DEAD_REGS: {  };
instr: 30
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:94 SP_BASE:16 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:94
    U6: OP: SPREAD_WT LINE:170 SP_BASE:6 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:170
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:6 VAR: tmp#24 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#24 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#72#||0 VAR: tmp#72 DATATYPE: HALF2,
    RF:4:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#72 DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( diffy43 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#24 == UNITRF_0_0[6] )
    //  IN:SP_SCHED_READ_0: ( tmp#76 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], diffy == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#72 == UNITRF_0_3[1] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy == SP_SCHED_RF_0[0] )
    DEAD_REGS: {  };
instr: 31
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:95 SP_BASE:17 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:95
    U6: OP: SPREAD_WT LINE:171 SP_BASE:7 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:171
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:5 VAR: tmp#25 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#25 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#76#||0 VAR: tmp#76 DATATYPE: HALF2,
    RF:3:IN:0:REG:2 = B:26 STAGE:1 VAR: tmp#76 DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( diffy43 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#25 == UNITRF_0_0[5] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy43 == SP_SCHED_RF_0[16] )
    //  IN:SP_SCHED_READ_0: ( tmp#78 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], diffy == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#76 == UNITRF_0_2[2] )
    DEAD_REGS: {  };
instr: 32
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:96 SP_BASE:18 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:96
    U6: OP: SPREAD_WT LINE:166 SP_BASE:2 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:166
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:4 VAR: tmp#26 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#26 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#78#||0 VAR: tmp#78 DATATYPE: HALF2,
    RF:3:IN:0:REG:1 = B:26 STAGE:1 VAR: tmp#78 DATATYPE: HALF2,
    //  IN:SP_SCHED_WRITE_0: ( diffy43 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#26 == UNITRF_0_0[4] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy43 == SP_SCHED_RF_0[16] )
    //  IN:SP_SCHED_READ_0: ( tmp#68 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], diffy == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#78 == UNITRF_0_2[1] )
    DEAD_REGS: {  };
instr: 33
    MC: OP: NONE LINE:-1,
    U6: OP: SPWRITE LINE:97 SP_BASE:19 SP_STAGE:1:0:0 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:97
    U6: OP: SPREAD_WT LINE:167 SP_BASE:3 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:167
    U5: OP: NSELECT LINE:-1 STAGE:1, // D:\working\im_apps\h264\corr_kc.i:-1
    B:7 = RF:17:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:2 = B:7 VAR: hw_const#0 DATATYPE: ANYINT,
    B:6 = RF:1:OUT:0:REG:3 VAR: tmp#27 DATATYPE: UNDEFINED,
    U6:IN:1 = B:6 VAR: tmp#27 DATATYPE: UNDEFINED,
    B:5 = RF:16:OUT:0:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U6:IN:0 = B:5 VAR: hw_const#0 DATATYPE: ANYINT,
    B:26 = U6:OUT:0 INSTR_LOG:2|tmp#68#||0 VAR: tmp#68 DATATYPE: HALF2,
    RF:4:IN:0:REG:2 = B:26 STAGE:1 VAR: tmp#68 DATATYPE: HALF2,
    B:39 = RF:18:OUT:2:REG:0 VAR: hw_const#0 DATATYPE: ANYINT,
    U5:IN:2 = B:39 VAR: hw_const#0 DATATYPE: ANYINT,
    B:10 = RF:6:OUT:0:REG:2 VAR: tmp#28 DATATYPE: UNDEFINED,
    U5:IN:0 = B:10 VAR: tmp#28 DATATYPE: UNDEFINED,
    B:28 = U5:OUT:0 INSTR_LOG:1|tmp#28#||0 VAR: tmp#28 DATATYPE: UNDEFINED,
    RF:1:IN:0:REG:3 = B:28 STAGE:1 VAR: tmp#28 DATATYPE: UNDEFINED,
    //  IN:SP_SCHED_WRITE_0: ( diffy43 ) = SPWRITE( hw_const#0 == SPIDXRF_1[0], tmp#27 == UNITRF_0_0[3] )
    // OUT:SP_SCHED_WRITE_0: SPWRITE => ( diffy43 == SP_SCHED_RF_0[16] )
    //  IN:SP_SCHED_READ_0: ( tmp#70 ) = SPREAD_WT( hw_const#0 == SPIDXRF_0[0], diffy == SP_SCHED_RF_0[0] )
    // OUT:SP_SCHED_READ_0: SPREAD_WT => ( tmp#68 == UNITRF_0_3[2] )