?? oled.lst
字號:
__start:
__text_start:
3E EFCF LDI R28,0xFF
3F E0D2 LDI R29,2
40 BFCD OUT 0x3D,R28
41 BFDE OUT 0x3E,R29
42 51C0 SUBI R28,0x10
43 40D0 SBCI R29,0
44 EA0A LDI R16,0xAA
45 8308 STD Y+0,R16
46 2400 CLR R0
47 E4E8 LDI R30,0x48
48 E0F1 LDI R31,1
49 E011 LDI R17,1
4A 34E9 CPI R30,0x49
4B 07F1 CPC R31,R17
4C F011 BEQ 0x004F
4D 9201 ST R0,Z+
4E CFFB RJMP 0x004A
4F 8300 STD Z+0,R16
50 E3E4 LDI R30,0x34
51 E0F0 LDI R31,0
52 E0A0 LDI R26,0
53 E0B1 LDI R27,1
54 E010 LDI R17,0
55 37EC CPI R30,0x7C
56 07F1 CPC R31,R17
57 F021 BEQ 0x005C
58 95C8 LPM
59 9631 ADIW R30,1
5A 920D ST R0,X+
5B CFF9 RJMP 0x0055
5C D001 RCALL _main
_exit:
5D CFFF RJMP _exit
_main:
Get_SO --> R10
5E 9721 SBIW R28,1
FILE: E:\sendavrnrf24l01\main.c
(0001) //ICC-AVR application builder : 2006-02-12 14:00:00
(0002) // Target : ATmega48
(0003) // Crystal: 8.000Mhz
(0004) // Author: jackyan
(0005) // Oled Type : white
(0006) //#define fosc 8000000
(0007) //#define baud 9600
(0008) #include "iom48v.h"
(0009) #include "macros.h"
(0010) #include "defs.h"
(0011) /*-----------------------------------------------------------------------------
(0012) Global Defines
(0013) ------------------------------------------------------------------------------*/
(0014) unsigned char key_debug;
(0015) unsigned char Buffer[]={
(0016) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0017) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0018) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0019) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0020) };
(0021) #define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width
(0022) #define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
(0023) unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
(0024) void init_CPU (void);
(0025) void delayms(unsigned short dly);//當dly=1時，延時的時間是1ms 4MHz晶震
(0026) void INIT_io(void);
(0027) void RX_Mode(void);
(0028) void TX_Mode(void);
(0029) void delay(void);
(0030) unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0031) unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0032) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
(0033) unsigned char SPI_Read(unsigned char reg);
(0034) void clear_buf(unsigned char *ptr,unsigned char number);
(0035) unsigned char accept_flag=0;
(0036) unsigned int accept_time=0;
(0037) //****************************************************************//
(0038) // SPI(nRF24L01) commands
(0039) #define READ_REG 0x00 // Define read command to register
(0040) #define WRITE_REG 0x20 // Define write command to register
(0041) #define RD_RX_PLOAD 0x61 // Define RX payload register address
(0042) #define WR_TX_PLOAD 0xA0 // Define TX payload register address
(0043) #define FLUSH_TX 0xE1 // Define flush TX register command
(0044) #define FLUSH_RX 0xE2 // Define flush RX register command
(0045) #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
(0046) //#define NOP 0xFF // Define No Operation, might be used to read status register
(0047) //***************************************************//
(0048) // SPI(nRF24L01) registers(addresses)
(0049) #define CONFIG 0x00 // 'Config' register address
(0050) #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
(0051) #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
(0052) #define SETUP_AW 0x03 // 'Setup address width' register address
(0053) #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
(0054) #define RF_CH 0x05 // 'RF channel' register address
(0055) #define RF_SETUP 0x06 // 'RF setup' register address
(0056) #define STATUS 0x07 // 'Status' register address
(0057) #define OBSERVE_TX 0x08 // 'Observe TX' register address
(0058) #define CD 0x09 // 'Carrier Detect' register address
(0059) #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
(0060) #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
(0061) #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
(0062) #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
(0063) #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
(0064) #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
(0065) #define TX_ADDR 0x10 // 'TX address' register address
(0066) #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
(0067) #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
(0068) #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
(0069) #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
(0070) #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
(0071) #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
(0072) #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
(0073) #define MAX_RT 0x10 // Max #of TX retrans interrupt
(0074) #define TX_DS 0x20 // TX data sent interrupt
(0075) #define RX_DR 0x40 // RX data received
(0076) //-----------------------------------------------------------------------------
(0077) //------------------------------------------------------
(0078) #define BIT(x) (1 << (x))
(0079) #define SETBIT(x, y) (x |= y)
(0080) #define CLEARBIT(x, y) (x &= ~y)
(0081) #define CHECKBIT(x, y) (x & y)
(0082) #define BIT7 0x80
(0083) #define BIT6 0x40
(0084) #define BIT5 0x20
(0085) #define BIT4 0x10
(0086) #define BIT3 0x08
(0087) #define BIT2 0x04
(0088) #define BIT1 0x02
(0089) #define BIT0 0x01
(0090) /*#define nRF24L01_CSN BIT4
(0091) #define nRF24L01_SCK BIT5
(0092) #define nRF24L01_MOSI BIT6
(0093) #define nRF24L01_CE BIT3
(0094) #define nRF24L01_MISO BIT7
(0095) #define nRF24L01_IRQ BIT0
(0096) #define nRF24L01_CSNH SETBIT(PORTD, BIT4)
(0097) #define nRF24L01_CSNL CLEARBIT(PORTD, BIT4)
(0098)
(0099) #define nRF24L01_SCKH SETBIT(PORTD,BIT5)
(0100) #define nRF24L01_SCKL CLEARBIT(PORTD,BIT5)
(0101)
(0102) #define nRF24L01_MOSIH SETBIT(PORTD,BIT6)
(0103) #define nRF24L01_MOSIL CLEARBIT(PORTD,BIT6)
(0104)
(0105) #define nRF24L01_CEH SETBIT(PORTD,BIT3)
(0106) #define nRF24L01_CEL CLEARBIT(PORTD,BIT3) */
(0107) //-----------------------------------------------------------------------------
(0108) #define nRF24L01_CSN BIT6
(0109) #define nRF24L01_SCK BIT1
(0110) #define nRF24L01_MOSI BIT0
(0111) #define nRF24L01_CE BIT7
(0112) #define nRF24L01_MISO BIT3
(0113) #define nRF24L01_IRQ BIT2
(0114) #define nRF24L01_CSNH SETBIT(PORTD, BIT6)
(0115) #define nRF24L01_CSNL CLEARBIT(PORTD, BIT6)
(0116)
(0117) #define nRF24L01_SCKH SETBIT(PORTB,BIT1)
(0118) #define nRF24L01_SCKL CLEARBIT(PORTB,BIT1)
(0119)
(0120) #define nRF24L01_MOSIH SETBIT(PORTB,BIT0)
(0121) #define nRF24L01_MOSIL CLEARBIT(PORTB,BIT0)
(0122)
(0123) #define nRF24L01_CEH SETBIT(PORTD,BIT7)
(0124) #define nRF24L01_CEL CLEARBIT(PORTD,BIT7)
(0125) //-----------------------------------------------------------------------------
(0126) void main(void)
(0127) {
(0128) unsigned char Get_SO=0;
5F 24AA CLR R10
(0129) CLI(); /* global interrupt disable */
60 94F8 BCLR 7
(0130) init_CPU ();
61 D076 RCALL _init_CPU
(0131) delayms(100); //延時10ms*10=100ms
62 E604 LDI R16,0x64
63 E010 LDI R17,0
64 D09B RCALL _delayms
(0132) delayms(100); //延時10ms*10=100ms
65 E604 LDI R16,0x64
66 E010 LDI R17,0
67 D098 RCALL _delayms
(0133) RX_Mode();
68 D10D RCALL _RX_Mode
69 C06B RJMP 0x00D5
(0134) while(1)
(0135) {
(0136) // if(!(PINB& 0x01))
(0137) if(!(PINB& 0x04))
6A 991A SBIC 0x03,2
6B C029 RJMP 0x0095
(0138) {//nRF24L01 接收數據
(0139) key_debug=SPI_Read(STATUS); // read register STATUS's value
6C E007 LDI R16,7
6D D0C8 RCALL _SPI_Read
6E 9300 0148 STS key_debug,R16
(0140) if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
70 FF06 SBRS R16,6
71 C006 RJMP 0x0078
(0141) SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
72 E184 LDI R24,0x14
73 8388 STD Y+0,R24
74 E020 LDI R18,0
75 E031 LDI R19,1
76 E601 LDI R16,0x61
77 D0CE RCALL _SPI_Read_Buf
(0142) if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
78 9020 0148 LDS R2,key_debug
7A FE24 SBRS R2,4
7B C003 RJMP 0x007F
7C 2722 CLR R18
7D EE01 LDI R16,0xE1
7E D0A9 RCALL _SPI_RW_Reg
(0143) SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
7F EF2F LDI R18,0xFF
80 E207 LDI R16,0x27
81 D0A6 RCALL _SPI_RW_Reg
(0144) RX_Mode();
82 D0F3 RCALL _RX_Mode
(0145) if((Buffer[0]==80)&&(Buffer[1]==01))//data accept
83 9180 0100 LDS R24,Buffer
85 3580 CPI R24,0x50
86 F471 BNE 0x0095
87 9180 0101 LDS R24,Buffer+1
89 3081 CPI R24,1
8A F451 BNE 0x0095
(0146) {
(0147) accept_flag=1;
8B E081 LDI R24,1
8C 9380 0145 STS accept_flag,R24
(0148) PORTC = 0x02;
8E E082 LDI R24,2
8F B988 OUT 0x08,R24
(0149) delayms(5000); //延時10ms*10=100ms
90 E808 LDI R16,0x88
91 E113 LDI R17,0x13
92 D06D RCALL _delayms
(0150) PORTC = 0x00;
93 2422 CLR R2
94 B828 OUT 0x08,R2
(0151) }
(0152) }
(0153) if(accept_flag==0)//data send
95 9020 0145 LDS R2,accept_flag
97 2022 TST R2
98 F4D1 BNE 0x00B3
(0154) {
(0155) accept_flag=1;
99 E081 LDI R24,1
9A 9380 0145 STS accept_flag,R24
(0156) accept_time=0;
9C 2422 CLR R2
9D 2433 CLR R3
9E 9230 0147 STS accept_time+1,R3
A0 9220 0146 STS accept_time,R2
(0157) Buffer[0]=80;
A2 E580 LDI R24,0x50
A3 9380 0100 STS Buffer,R24
(0158) Buffer[1]=02;
A5 E082 LDI R24,2
A6 9380 0101 STS Buffer+1,R24
(0159) TX_Mode(); // set TX Mode and transmitting
A8 D0EC RCALL _TX_Mode
(0160) Buffer[0]=80;
A9 E580 LDI R24,0x50
AA 9380 0100 STS Buffer,R24
(0161) Buffer[1]=02;
AC E082 LDI R24,2
AD 9380 0101 STS Buffer+1,R24
(0162) TX_Mode(); // set TX Mode and transmitting
AF D0E5 RCALL _TX_Mode
(0163) delayms(100);
B0 E604 LDI R16,0x64
B1 E010 LDI R17,0
B2 D04D RCALL _delayms
(0164) }
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