#! /usr/local/bin/perl################################################################################## Copyright (c) 2000 - 2007 X-Tek Corporation## This script will read your VHDL or Verilog component library files and create # a database that X-HDL 4.0 can use for the component instantiations. Perform the # following steps to use a pre-defined library:## 1) cd to the directory containing the VHDL or Verilog component library: #      % cd ..../my_lib## 2) run the make_lib script on the library files: #       % make_lib -vhdl vhdl_file1.vhd vhdl_file2.vhd ....## make_lib will create a directory called .xhdl in the my_lib directory. Within the# .xhdl directory will be a database file for each component processed. These # database files are subsequently used by X-HDL when the components are instantiated.## Use make_lib -h to get help with the make_lib command line options## 3) Run X-HDL as usual. In the Translate menu, enter the information for the pre-defined# library in the 'Database Paths' list (or -db command-line option). The library # name can be whatever you want (this will be translated to a LIBRARY statement in VHDL). # The database path needs to be the path to the pre-defined VHDL, ie .../my_lib## 4) The pre-defined components will be found and instantiated. ###  Revision History#     Rev 1.6 - Mar. 19, 2007#        - Modified to generate new format X-HDL 4.0 database#     Rev 1.5 - Sep. 28, 2005#        - Modified to generate X-HDL 4.0 style database#     Rev 1.4 - May 21, 2002#        - Forced all library entry names to be lower-case for Verilog libraries#     Rev 1.3 - July 11, 2000#        - Added the command line option -l which forces all VHDL port names to be#          lower-case. In previous versions, this was the default, and only, #          operation. The default is now to leave port names as-is.#################################################################################use English;use strict;my $Revision = '1.6 Mar. 19, 2007';(my $myself = $0) =~ s/.*\/(\w+).*/$1/;# setup default optionsmy $lang = 'vhdl';my $lowercase = 0;my $lib = {};# process command line optionsmy $opt;while ($ARGV[0] =~ /^\-/) {	$opt = shift;	$lang = 'vlog' if ($opt eq '-vlog');	$lang = 'vhdl' if ($opt eq '-vhdl');   $lowercase = 1 if ($opt eq '-l');	&usage if ($opt eq '-h' || $opt !~ /^\-(h|l|vlog|vhdl)$/);}# create database directory if it does not existmkdir ".xhdl" if (!-e ".xhdl");$INPUT_RECORD_SEPARATOR = undef;# process in the specified filesmy ($text, $dirname, $file);while ($file = shift @ARGV) {	unless (open(CODE, "< $file")) {		print STDERR "Cannot open file $file for reading - skipping\n";		next;	}		# read code from file	$text = <CODE>;	close CODE;		# process a vhdl library   my $lib = {};	if ($lang eq 'vhdl') {		# strip all comments from the code		$text =~ s/\-\-.*?\n/\n/sg;		# grab the next entity		my ($name, $entity, @ports, $dir, $port, $component, $entity_name, $generic, @generics, $gen);		while ($text =~ s/^.*?\bentity\s+(\w+)\s+is//si) {			$name = "\L$1\E";			$entity_name = $1;			$text =~ s/^(.*?)end\s+(entity\s+)?${name}//si;			$entity = $component = $1;			$component =~ s/(^.*\b)(port\s*\()/$2/si;         $generic = $1;         $generic =~ s/^.*\b(generic\s*\()/$1/si;			$generic =~ s/\n//sg;         @generics = split(/\;/, $generic);			foreach my $g (@generics) {				if ($g =~ /\s*(\w+)\s*\:\s*(\w+)/) {					$gen = ($lowercase) ? "\L$1\E" : $1;					push(@{$lib->{$name}->{generics}}, {-val => $gen, -name => $gen});				}			}			$component =~ s/\battribute.*?\;//sgi;			1 while ($component =~ s/\n\s*\n/\n/s);			$component =~ s/\n\n/\n/sg;			$component = "component $entity_name " . $component . "end component;\n";			$entity =~ s/^.*?\bport\s*\(//si;			$entity =~ s/\n//sg;			@ports = split(/\;/, $entity);			foreach my $p (@ports) {				if ($p =~ /\s*(\w+)\s*\:\s*(\w+)/) {					$port = ($lowercase) ? "\L$1\E" : $1;					$dir = "\L$2\E";					$dir = ($dir =~ /^in$/) ? 'input' : ($dir =~ /^out$/) ? 'output' : ($dir =~ /^(inout|buffer)$/) ? 'inout' : '';					push(@{$lib->{$name}->{io}}, {-val => $port, -name => $port, -dir => $dir});				}			}			$lib->{$name}->{entity} = $name;			$lib->{$name}->{component} = $component;		}		# process a verilog library	} else {		# strip all comments from the code		$text =~ s/\/\/.*?\n/\n/sg;		$text =~ s/\/\*.*?\*\///sg;		# grab the next module		my ($name, @ports, $port_list, $port);		while ($text =~ s/^.*?\bmodule\s+(\w+)\s*\((.*?)\)//si) {         $name = $1;			my $lc_name = "\L$name\E";			$port_list = $2;			$port_list =~ s/\s//gs;			@ports = split(/\,/, $port_list);			foreach $port (@ports) {				push(@{$lib->{$lc_name}->{io}}, {-val => $port, -name => $port, -dir => ''});			}			$lib->{$lc_name}->{entity} = $name;		}	}   # output database   foreach my $dbname (keys %{$lib})   {      open(LIB, "> .xhdl/$dbname") || die "Cannot open .xhdl/$dbname for writing - database not created\n";            # output component data      print LIB "[Data]\n";      if ($lang eq 'vhdl') {         my $comp = $lib->{$dbname}->{component};         $comp =~ s/\n/\\n/g;         print LIB '%3Ccompdecl%3E="' . $comp . "\\n\"\n";      }      print LIB '%3CgenericOrder%3E=';      if (!defined($lib->{$dbname}->{generics})) {         print LIB '@Invalid()' . "\n";      } else {         my @generics;         foreach my $gen (@{$lib->{$dbname}->{generics}}) {            push (@generics, $gen->{-name});         }         print LIB join(", ", @generics) . "\n";      }      print LIB '%3CportOrder%3E=';      if (!defined($lib->{$dbname}->{io})) {         print LIB '@Invalid()' . "\n";      } else {         my @ports;         foreach my $io (@{$lib->{$dbname}->{io}}) {            push (@ports, $io->{-name});         }         print LIB join(", ", @ports) . "\n";      }      foreach my $gen (@{$lib->{$dbname}->{generics}}) {         my $name = $gen->{-name};         print LIB "$name\\alias=$name\n";         print LIB "$name\\category=";         print LIB (($lang eq 'vhdl') ? "109\n" : "111\n");         print LIB "$name\\port=0\n";      }      foreach my $io (@{$lib->{$dbname}->{io}}) {         my $name = $io->{-name};         print LIB "$name\\alias=$name\n";         print LIB "$name\\category=";         print LIB (($lang eq 'vhdl') ? "114\n" : "117\n");         print LIB "$name\\port=1\n";      }      print LIB "\n";            # output general information      print LIB '[%General]' . "\n";      print LIB '%3Cbasename%3E=' . "$dbname\n";      print LIB '%3Cclass%3E=108' . "\n";      print LIB '%3Cfilename%3E=' . "$file\n";      print LIB '%3Cpackage%3E=false' . "\n";      print LIB '%3Csource%3E=' . "\n";            close LIB;   }}sub usage {   print STDERR "\nThis is $myself $Revision running under Perl version $PERL_VERSION\n\n";   print STDERR "usage: $myself [-vhdl/-vlog] [-l] file [file...]\n\n";   print STDERR "       -vhdl  => create a VHDL library (default)\n";   print STDERR "       -vlog  => create a Verilog library\n";   print STDERR "       -l     => lower-case VHDL component port names. Default: Leave as-is\n";   print STDERR "       -h     => Print this message\n";   print STDERR "\n";   exit(-1);}