---- Copyright Notice and Proprietary Information---- Copyright (C) 1997-2002 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be used only as -- authorized in the license agreement controlling such use. No part of this -- publication may be reproduced, transmitted, or translated, in any form or by -- any means, electronic, mechanical, manual, optical, or otherwise, without prior -- written permission of X-Tek Corporation, or as expressly provided by the license -- agreement.---- Disclaimer---- X-Tek Corporation makes no warranty of any kind, express or implied, with regard -- to this material, including, but not limited to, the implied warranties of -- merchantability and fitness for a particular purpose.---- X-Tek Corporation reserves the right to make changes without further notice to -- the products described herein. X-Tek Corporation does not assume any liability -- arising out of the application or use of any product or circuit described -- herein. The X-Tek products described herein are not authorized for use as -- components in life-support devices.------ Rev 2001.0226---- Rev 2001.0324--    a) Added function    --          FUNCTION conv_std_logic_vector (--             val      : IN boolean;--             len      : IN integer) RETURN std_logic_vector;---- Rev 2002.0521--    a) Removed non-synthesizable functions to_time and to_*string--LIBRARY ieee;USE ieee.std_logic_1164.all;LIBRARY std;USE std.textio.all;PACKAGE xhdl_std_logic IS   FUNCTION to_stdlogic (      val      : IN boolean) RETURN std_logic;         FUNCTION conv_std_logic (      val      : IN boolean) RETURN std_logic;         FUNCTION conv_std_logic (      val      : IN integer) RETURN std_logic;         FUNCTION conv_std_logic_vector (      val      : IN boolean;      len      : IN integer) RETURN std_logic_vector;        FUNCTION conv_std_logic_vector (      val      : IN integer;      len      : IN integer) RETURN std_logic_vector;        FUNCTION to_stdlogicvector (      val      : IN integer;      len      : IN integer) RETURN std_logic_vector;   FUNCTION to_stdlogicvector (      val      : IN boolean;      len      : IN integer) RETURN std_logic_vector;   FUNCTION to_integer (      val      : std_logic) RETURN integer;         FUNCTION to_integer (      val      : std_logic_vector) RETURN integer;         FUNCTION "SRL" (      l        : std_logic_vector;      r        : integer) RETURN std_logic_vector;      FUNCTION ShiftRight (      val      : std_logic_vector;      shft     : integer) RETURN std_logic_vector;      FUNCTION "SLL" (      l        : std_logic_vector;      r        : integer) RETURN std_logic_vector;      FUNCTION ShiftLeft (      val      : std_logic_vector;      shft     : integer) RETURN std_logic_vector;      FUNCTION "+" (      l        : std_logic;      r        : std_logic) RETURN std_logic_vector;      --       FUNCTION or_br (      val : std_logic_vector) RETURN std_logic;      FUNCTION and_br (      val : std_logic_vector) RETURN std_logic;   FUNCTION xor_br (      val : std_logic_vector) RETURN std_logic;   FUNCTION xnor_br (      val : std_logic_vector) RETURN std_logic;   FUNCTION nor_br (      val : std_logic_vector) RETURN std_logic;   FUNCTION nand_br (      val : std_logic_vector) RETURN std_logic;   FUNCTION select_expr (      sel : boolean;      op1 : std_logic_vector;      op2 : std_logic_vector) RETURN std_logic_vector;   FUNCTION select_expr (      sel : boolean;      op1 : std_logic;      op2 : std_logic) RETURN std_logic;END;PACKAGE BODY xhdl_std_logic IS   FUNCTION to_stdlogic (      val      : IN boolean) RETURN std_logic IS   BEGIN      IF (val) THEN         RETURN('1');      ELSE         RETURN('0');      END IF;   END to_stdlogic;      FUNCTION conv_std_logic (      val      : IN boolean) RETURN std_logic IS   BEGIN      RETURN(to_stdlogic(val));   END conv_std_logic;   FUNCTION conv_std_logic (      val      : IN integer) RETURN std_logic IS   BEGIN      IF (val = 1) THEN         RETURN('1');      ELSE         RETURN('0');      END IF;   END conv_std_logic;   FUNCTION conv_std_logic_vector (      val      : IN boolean;      len      : IN integer) RETURN std_logic_vector IS            VARIABLE rtn      : std_logic_vector(len-1 DOWNTO 0) := (OTHERS => '0');      VARIABLE b        : std_logic;   BEGIN      IF (val) THEN         b := '1';      ELSE         b := '0';      END IF;      FOR index IN 0 TO len-1 LOOP         rtn(index) := b;      END LOOP;	   RETURN(rtn);	END conv_std_logic_vector;   FUNCTION conv_std_logic_vector (      val      : IN integer;      len      : IN integer) RETURN std_logic_vector IS   BEGIN	   RETURN(to_stdlogicvector(val, len));	END conv_std_logic_vector;   --      FUNCTION to_stdlogicvector (      val      : IN integer;      len      : IN integer) RETURN std_logic_vector IS            VARIABLE rtn      : std_logic_vector(len-1 DOWNTO 0) := (OTHERS => '0');      VARIABLE num      : integer := val;      VARIABLE r        : integer;   BEGIN      FOR index IN 0 TO len-1 LOOP         r := num rem 2;         num := num/2;         IF (r = 1) THEN            rtn(index) := '1';         ELSE            rtn(index) := '0';         END IF;      END LOOP;      RETURN(rtn);   END to_stdlogicvector;            --            FUNCTION to_stdlogicvector (      val      : IN boolean;      len      : IN integer) RETURN std_logic_vector IS            VARIABLE rtn      : std_logic_vector(len-1 DOWNTO 0) := (OTHERS => '0');   BEGIN      rtn(0) := to_stdlogic(val);      RETURN(rtn);   END to_stdlogicvector;            --           FUNCTION to_integer (      val      : std_logic) RETURN integer IS      VARIABLE rtn      : integer := 0;   BEGIN      IF (val = '1') THEN         rtn := 1;      ELSE         rtn := 0;      END IF;      RETURN(rtn);   END to_integer;                     --     FUNCTION to_integer (      val      : std_logic_vector) RETURN integer IS      CONSTANT vec      : std_logic_vector(val'high-val'low DOWNTO 0) := val;            VARIABLE rtn      : integer := 0;   BEGIN      FOR index IN vec'RANGE LOOP         IF (vec(index) = '1') THEN            rtn := rtn + (2**index);         END IF;      END LOOP;      RETURN(rtn);   END to_integer;                     --   FUNCTION "SRL" (      l        : std_logic_vector;      r        : integer) RETURN std_logic_vector IS   BEGIN      RETURN(ShiftRight(l, r));   END "SRL";      FUNCTION ShiftRight (      val      : std_logic_vector;      shft     : integer) RETURN std_logic_vector IS            VARIABLE int      : std_logic_vector(val'LENGTH+shft-1 DOWNTO 0);      VARIABLE rtn      : std_logic_vector(val'RANGE);      VARIABLE fill     : std_logic_vector(shft-1 DOWNTO 0) := (others => '0');   BEGIN      int := fill & val;      rtn := int(val'LENGTH+shft-1 DOWNTO shft);      RETURN(rtn);   END ShiftRight;                     --   FUNCTION "SLL" (      l        : std_logic_vector;      r        : integer) RETURN std_logic_vector IS   BEGIN      RETURN(ShiftLeft(l, r));   END "SLL";      FUNCTION ShiftLeft (      val      : std_logic_vector;      shft     : integer) RETURN std_logic_vector IS            VARIABLE int      : std_logic_vector(val'LENGTH+shft-1 DOWNTO 0);      VARIABLE rtn      : std_logic_vector(val'RANGE);      VARIABLE fill     : std_logic_vector(shft-1 DOWNTO 0) := (others => '0');   BEGIN      int := val & fill;      rtn := int(val'LENGTH-1 DOWNTO 0);      RETURN(rtn);   END ShiftLeft;                  FUNCTION "+" (      l        : std_logic;      r        : std_logic) RETURN std_logic_vector IS            VARIABLE rtn      : std_logic_vector(1 downto 0);      VARIABLE tmp      : std_logic_vector(1 downto 0);   BEGIN      tmp := l & r;      CASE tmp IS         WHEN "00"   => rtn := "00";         WHEN "01"   => rtn := "01";         WHEN "10"   => rtn := "01";         WHEN "11"   => rtn := "10";         WHEN OTHERS => rtn := "XX";      END CASE;      RETURN(rtn);   END "+";         --    FUNCTION or_br (      val : std_logic_vector) RETURN std_logic IS         VARIABLE rtn : std_logic := '0';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn OR val(index);      END LOOP;      RETURN(rtn);   END or_br;   --      FUNCTION and_br (      val : std_logic_vector) RETURN std_logic IS      VARIABLE rtn : std_logic := '1';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn AND val(index);      END LOOP;      RETURN(rtn);   END and_br;   --      FUNCTION xor_br (      val : std_logic_vector) RETURN std_logic IS      VARIABLE rtn : std_logic := '0';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn XOR val(index);      END LOOP;      RETURN(rtn);   END xor_br;   --      FUNCTION xnor_br (      val : std_logic_vector) RETURN std_logic IS      VARIABLE rtn : std_logic := '0';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn XOR val(index);      END LOOP;      RETURN(NOT rtn);   END xnor_br;   --   FUNCTION nor_br (      val : std_logic_vector) RETURN std_logic IS      VARIABLE rtn : std_logic := '0';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn OR val(index);      END LOOP;      RETURN(NOT rtn);   END nor_br;   --   FUNCTION nand_br (      val : std_logic_vector) RETURN std_logic IS      VARIABLE rtn : std_logic := '0';   BEGIN      FOR index IN val'RANGE LOOP         rtn := rtn AND val(index);      END LOOP;      RETURN(NOT rtn);   END nand_br;   --   FUNCTION select_expr (      sel : boolean;      op1 : std_logic_vector;      op2 : std_logic_vector) RETURN std_logic_vector IS      VARIABLE rtn      : std_logic_vector(op1'RANGE);   BEGIN      IF(sel) THEN         rtn := op1;      ELSE         rtn := op2;      END IF;            RETURN (rtn);   END select_expr;   --   FUNCTION select_expr (      sel : boolean;      op1 : std_logic;      op2 : std_logic) RETURN std_logic IS      VARIABLE rtn      : std_logic;   BEGIN      IF(sel) THEN         rtn := op1;      ELSE         rtn := op2;      END IF;            RETURN (rtn);   END select_expr;END;