endendtasktask test_full_fifo_ext;  begin    release_rx_buffer;    $display("\n\n");    read_receive_buffer;    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h0, 15'h6f54); // mode, rtr, id, length, crc    read_receive_buffer;    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h1, 15'h6d38); // mode, rtr, id, length, crc    read_receive_buffer;    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h2, 15'h053e); // mode, rtr, id, length, crc    fifo_info;    read_receive_buffer;    receive_frame(1, 0, 29'h14d60246, 4'h3, 15'h5262); // mode, rtr, id, length, crc    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h4, 15'h4bba); // mode, rtr, id, length, crc    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h5, 15'h4d7d); // mode, rtr, id, length, crc    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h6, 15'h6f40); // mode, rtr, id, length, crc    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h7, 15'h1730); // mode, rtr, id, length, crc    fifo_info;    read_overrun_info(0, 10);    release_rx_buffer;    release_rx_buffer;    fifo_info;    receive_frame(1, 0, 29'h14d60246, 4'h8, 15'h2f7a); // mode, rtr, id, length, crc    fifo_info;    read_overrun_info(0, 15);    $display("\n\n");    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;    release_rx_buffer;    read_receive_buffer;    fifo_info;  endendtasktask initialize_fifo;  integer i;  begin    for (i=0; i<32; i=i+1)      begin        can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i] = 0;        can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i] = 0;      end    for (i=0; i<64; i=i+1)      begin        can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo[i] = 0;      end    $display("(%0t) Fifo initialized", $time);  endendtasktask read_overrun_info;  input [4:0] start_addr;  input [4:0] end_addr;  integer i;  begin    for (i=start_addr; i<=end_addr; i=i+1)      begin        $display("len[0x%0x]=0x%0x", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.length_info[i]);        $display("overrun[0x%0x]=0x%0x\n", i, can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[i]);      end  endendtasktask fifo_info;   // Displaying how many packets and how many bytes are in fifo. Not working when wr_info_pointer is smaller than rd_info_pointer.  begin      $display("(%0t) Currently %0d bytes in fifo (%0d packets)", $time, can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_cnt,       (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr_info_pointer - can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer));endendtasktask read_register;  input [7:0] reg_addr;  begin    @ (posedge wb_clk_i);    #1;     wb_adr_i = reg_addr;    wb_cyc_i = 1;    wb_stb_i = 1;    wb_we_i = 0;    wait (wb_ack_o);    $display("(%0t) Reading register [%0d] = 0x%0x", $time, wb_adr_i, wb_dat_o);    @ (posedge wb_clk_i);    #1;     wb_adr_i = 'hz;    wb_cyc_i = 0;    wb_stb_i = 0;    wb_we_i = 'hz;  endendtasktask write_register;  input [7:0] reg_addr;  input [7:0] reg_data;  begin    @ (posedge wb_clk_i);    #1;     wb_adr_i = reg_addr;    wb_dat_i = reg_data;    wb_cyc_i = 1;    wb_stb_i = 1;    wb_we_i = 1;    wait (wb_ack_o);    @ (posedge wb_clk_i);    #1;     wb_adr_i = 'hz;    wb_dat_i = 'hz;    wb_cyc_i = 0;    wb_stb_i = 0;    wb_we_i = 'hz;  endendtasktask read_receive_buffer;  integer i;  begin    if(`CAN_CLOCK_DIVIDER_MODE)   // Extended mode      begin        for (i=8'd16; i<=8'd28; i=i+1)          read_register(i);        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])          $display("\nWARNING: This packet was received with overrun.");      end    else      begin        for (i=8'd20; i<=8'd29; i=i+1)          read_register(i);        if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.overrun_info[can_testbench.i_can_top.i_can_bsp.i_can_fifo.rd_info_pointer])          $display("\nWARNING: This packet was received with overrun.");      end  endendtasktask release_rx_buffer;  begin    write_register(8'd1, 8'h4);    $display("(%0t) Rx buffer released.", $time);  endendtasktask tx_request;  begin    write_register(8'd1, 8'h1);    $display("(%0t) Tx requested.", $time);  endendtasktask test_synchronization;  begin    // Hard synchronization    #1 rx=0;    repeat (2*BRP) @ (posedge clk);    repeat (8*BRP) @ (posedge clk);    #1 rx=1;    repeat (10*BRP) @ (posedge clk);      // Resynchronization on time    #1 rx=0;    repeat (10*BRP) @ (posedge clk);    #1 rx=1;    repeat (10*BRP) @ (posedge clk);      // Resynchronization late    repeat (BRP) @ (posedge clk);    repeat (BRP) @ (posedge clk);    #1 rx=0;    repeat (10*BRP) @ (posedge clk);    #1 rx=1;      // Resynchronization early    repeat (8*BRP) @ (posedge clk);   // two frames too early    #1 rx=0;    repeat (10*BRP) @ (posedge clk);    #1 rx=1;    repeat (10*BRP) @ (posedge clk);  endendtasktask send_bit;  input bit;  integer cnt;  begin    #1 rx=bit;    repeat ((`CAN_TIMING1_TSEG1 + `CAN_TIMING1_TSEG2 + 3)*BRP) @ (posedge clk);  endendtasktask receive_frame;           // CAN IP core receives frames  input mode;  input remote_trans_req;  input [28:0] id;  input  [3:0] length;  input [14:0] crc;  reg [117:0] data;  reg         previous_bit;  reg         stuff;  reg         tmp;  reg         arbitration_lost;  integer     pointer;  integer     cnt;  integer     total_bits;  integer     stuff_cnt;  begin    stuff_cnt = 1;    stuff = 0;    if(mode)          // Extended format      data = {id[28:18], 1'b1, 1'b1, id[17:0], remote_trans_req, 2'h0, length};    else              // Standard format      data = {id[10:0], remote_trans_req, 1'b0, 1'b0, length};    if (~remote_trans_req)      begin        if(length)    // Send data if length is > 0          begin            for (cnt=1; cnt<=(2*length); cnt=cnt+1)  // data   (we are sending nibbles)              data = {data[113:0], cnt[3:0]};          end      end    // Adding CRC    data = {data[104:0], crc[14:0]};    // Calculating pointer that points to the bit that will be send    if (remote_trans_req)      begin        if(mode)          // Extended format          pointer = 52;        else              // Standard format          pointer = 32;      end    else      begin        if(mode)          // Extended format          pointer = 52 + 8 * length;        else              // Standard format          pointer = 32 + 8 * length;      end    // This is how many bits we need to shift    total_bits = pointer;    // Waiting until previous msg is finished before sending another one    wait (~can_testbench.i_can_top.i_can_bsp.error_frame & ~can_testbench.i_can_top.i_can_bsp.rx_inter & ~can_testbench.i_can_top.i_can_bsp.tx_state);    arbitration_lost = 0;        send_bit(0);                        // SOF    previous_bit = 0;    fork     begin      while (~arbitration_lost)        begin          for (cnt=0; cnt<=total_bits; cnt=cnt+1)            begin              if (stuff_cnt == 5)                begin                  stuff_cnt = 1;                  total_bits = total_bits + 1;                  stuff = 1;                  tmp = ~data[pointer+1];                  send_bit(~data[pointer+1]);                  previous_bit = ~data[pointer+1];                end              else                begin                  if (data[pointer] == previous_bit)                    stuff_cnt <= stuff_cnt + 1;                  else                    stuff_cnt <= 1;                                    stuff = 0;                  tmp = data[pointer];                  send_bit(data[pointer]);                  previous_bit = data[pointer];                  pointer = pointer - 1;                end              if (arbitration_lost)                cnt=total_bits+1;         // Exit the for loop            end            arbitration_lost = 1; // At the end we exit the while loop            // Nothing send after the data (just recessive bit)            repeat (13) send_bit(1);         // CRC delimiter + ack + ack delimiter + EOF + intermission= 1 + 1 + 1 + 7 + 3        end    end    begin      while (~arbitration_lost)        begin          #1 wait (can_testbench.i_can_top.sample_point);          if (mode)            begin              if (cnt<32 & tmp & (~rx_and_tx))                begin                  arbitration_lost = 1;                  rx = 1;       // Only recessive is send from now on.                end            end          else            begin              if (cnt<12 & tmp & (~rx_and_tx))                begin                  arbitration_lost = 1;                  rx = 1;       // Only recessive is send from now on.                end            end        end    end    join  endendtask// State machine monitor (btl)always @ (posedge clk)begin  if(can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg1 | can_testbench.i_can_top.i_can_btl.go_sync & can_testbench.i_can_top.i_can_btl.go_seg2 |      can_testbench.i_can_top.i_can_btl.go_seg1 & can_testbench.i_can_top.i_can_btl.go_seg2)    begin      $display("(%0t) ERROR multiple go_sync, go_seg1 or go_seg2 occurance\n\n", $time);      #1000;      $stop;    end  if(can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg1 | can_testbench.i_can_top.i_can_btl.sync & can_testbench.i_can_top.i_can_btl.seg2 |      can_testbench.i_can_top.i_can_btl.seg1 & can_testbench.i_can_top.i_can_btl.seg2)    begin      $display("(%0t) ERROR multiple sync, seg1 or seg2 occurance\n\n", $time);      #1000;      $stop;    endend/* stuff_error monitor (bsp)always @ (posedge clk)begin  if(can_testbench.i_can_top.i_can_bsp.stuff_error)    begin      $display("\n\n(%0t) Stuff error occured in can_bsp.v file\n\n", $time);      $stop;                                      After everything is finished add another condition (something like & (~idle)) and enable stop    endend*///// CRC monitor (used until proper CRC generation is used in testbenchalways @ (posedge clk)begin  if (can_testbench.i_can_top.i_can_bsp.crc_err)    $display("Calculated crc = 0x%0x, crc_in = 0x%0x", can_testbench.i_can_top.i_can_bsp.calculated_crc, can_testbench.i_can_top.i_can_bsp.crc_in);end///*// overrun monitoralways @ (posedge clk)begin  if (can_testbench.i_can_top.i_can_bsp.i_can_fifo.wr & can_testbench.i_can_top.i_can_bsp.i_can_fifo.fifo_full)    $display("(%0t)overrun", $time);end*/// form error monitoralways @ (posedge clk)begin  if (can_testbench.i_can_top.i_can_bsp.form_err)    $display("\n\n(%0t) ERROR: form_error\n\n", $time);end//endmodule