library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; 
use ieee.std_logic_arith.all;

entity can_registers is
port (

         clk :    in std_logic;
         rst :    in std_logic;
         cs  :    in std_logic;
         we  :    in std_logic;
         addr:    in std_logic_vector(7 downto 0);
         data_in: in std_logic_vector(7 downto 0);
        
         data_out: out std_logic_vector(7 downto 0);

        

-- Mode register 
         reset_mode:             out std_logic;
         listen_only_mode:       out std_logic;
         acceptance_filter_mode: out std_logic;
         sleep_mode:             out std_logic;

-- Command register 
         clear_data_overrun: out std_logic;
         release_buffer:     out std_logic;
         abort_tx:           out std_logic;
         tx_request:         out std_logic;
         self_rx_request:    out std_logic;

-- Bus Timing 0 register 
         baud_r_presc:    out std_logic_vector(5 downto 0);
         sync_jump_width: out std_logic_vector(1 downto 0);


-- Bus Timing 1 register 
         time_segment1:   out std_logic_vector(3 downto 0);
         time_segment2:   out std_logic_vector(2 downto 0);
         triple_sampling: out std_logic;
        
-- Clock Divider register 
         extended_mode: out std_logic;
         rx_int_enable: out std_logic;
         clock_off:     out std_logic;
         cd:            out std_logic_vector(2 downto 0);
        

-- This section is for BASIC and EXTENDED mode 
-- Acceptance code register 
        acceptance_code_0: out std_logic_vector(7 downto 0);

-- Acceptance mask register 
        acceptance_mask_0: out std_logic_vector(7 downto 0);

-- End: This section is for BASIC and EXTENDED mode 


-- This section is for EXTENDED mode 
-- Acceptance code register 
       acceptance_code_1: out std_logic_vector(7 downto 0);
       acceptance_code_2: out std_logic_vector(7 downto 0);
       acceptance_code_3: out std_logic_vector(7 downto 0);

-- Acceptance mask register 
       acceptance_mask_1: out std_logic_vector(7 downto 0);
       acceptance_mask_2: out std_logic_vector(7 downto 0);
       acceptance_mask_3: out std_logic_vector(7 downto 0);

-- End: This section is for EXTENDED mode 

-- Tx data registers. Holding identifier (basic mode), tx frame information (extended mode) and data 
       tx_data_0 : out std_logic_vector(7 downto 0) ;
       tx_data_1 : out std_logic_vector(7 downto 0) ;
       tx_data_2 : out std_logic_vector(7 downto 0) ;
       tx_data_3 : out std_logic_vector(7 downto 0) ;
       tx_data_4 : out std_logic_vector(7 downto 0) ;
       tx_data_5 : out std_logic_vector(7 downto 0) ;
       tx_data_6 : out std_logic_vector(7 downto 0) ;
       tx_data_7 : out std_logic_vector(7 downto 0) ;
       tx_data_8 : out std_logic_vector(7 downto 0) ;
       tx_data_9 : out std_logic_vector(7 downto 0) ;
       tx_data_10: out std_logic_vector(7 downto 0) ;
       tx_data_11: out std_logic_vector(7 downto 0) ;
       tx_data_12: out std_logic_vector(7 downto 0));
--End: Tx data registers 

end can_registers;

architecture RTL of can_registers is

component can_register_asyn_syn is
generic(
         WIDTH       : integer := 8 ;
         RESET_VALUE : integer := 0);
port        
(
      data_in  : in std_logic_vector(WIDTH-1 downto 0)   ;
      we       : in std_logic                            ;
      clk      : in std_logic                            ;
      rst      : in std_logic                            ;
      rst_sync : in std_logic                            ;

      data_out :  out std_logic_vector(WIDTH-1 downto 0));
end component;

component can_register_asyn is
generic(
         WIDTH       : integer := 8 ;
         RESET_VALUE : integer := 0);
port        
(
      data_in  : in std_logic_vector(WIDTH-1 downto 0)   ;
      we       : in std_logic                            ;
      clk      : in std_logic                            ;
      rst      : in std_logic                            ;

      data_out :  out std_logic_vector(WIDTH-1 downto 0));
end component;

component can_register is
generic(
         WIDTH: integer := 8
        );
port        
(
      data_in  : in std_logic_vector(WIDTH-1 downto 0);
      we       : in std_logic;
      clk      : in std_logic;

      data_out :  out std_logic_vector(WIDTH-1 downto 0)
);
end component;

signal we_mode                   :std_logic;
signal we_command                :std_logic;
signal we_bus_timing_0           :std_logic;
signal we_bus_timing_1      :std_logic;
signal we_clock_divider_low :std_logic;
signal we_clock_divider_hi  :std_logic;

signal read                      :std_logic;


-- This section is for BASIC and EXTENDED mode 
signal we_acceptance_code_0       :std_logic;
signal we_acceptance_mask_0       :std_logic;
signal we_tx_data_0               :std_logic;
signal we_tx_data_1               :std_logic;
signal we_tx_data_2               :std_logic;
signal we_tx_data_3               :std_logic;
signal we_tx_data_4               :std_logic;
signal we_tx_data_5               :std_logic;
signal we_tx_data_6               :std_logic;
signal we_tx_data_7               :std_logic;
signal we_tx_data_8               :std_logic;
signal we_tx_data_9               :std_logic;
signal we_tx_data_10              :std_logic;
signal we_tx_data_11              :std_logic;
signal we_tx_data_12              :std_logic;
                                  
-- End: This section is for BASIC and EXTENDED mode 
                                  

-- This section is for EXTENDED mode 
signal we_acceptance_code_1     :std_logic;
signal we_acceptance_code_2     :std_logic;
signal we_acceptance_code_3     :std_logic;
signal we_acceptance_mask_1     :std_logic;
signal we_acceptance_mask_2     :std_logic;
signal we_acceptance_mask_3     :std_logic;
-- End: This section is for EXTENDED mode 

signal mode   :               std_logic_vector(7 downto 0);
signal command:               std_logic_vector(4 downto 0);
signal bus_timing_0:          std_logic_vector(7 downto 0);
signal bus_timing_1:          std_logic_vector(7 downto 0);
signal clock_divider:         std_logic_vector(7 downto 0);
signal acceptance_code_0_reg: std_logic_vector(7 downto 0);
signal acceptance_code_1_reg: std_logic_vector(7 downto 0);
signal acceptance_code_2_reg: std_logic_vector(7 downto 0);
signal acceptance_code_3_reg: std_logic_vector(7 downto 0);
signal acceptance_mask_0_reg: std_logic_vector(7 downto 0);
signal acceptance_mask_1_reg: std_logic_vector(7 downto 0);
signal acceptance_mask_2_reg: std_logic_vector(7 downto 0);
signal acceptance_mask_3_reg: std_logic_vector(7 downto 0);

signal tx_data_0_reg  : std_logic_vector(7 downto 0);
signal tx_data_1_reg  : std_logic_vector(7 downto 0);
signal tx_data_2_reg  : std_logic_vector(7 downto 0);
signal tx_data_3_reg  : std_logic_vector(7 downto 0);
signal tx_data_4_reg  : std_logic_vector(7 downto 0);
signal tx_data_5_reg  : std_logic_vector(7 downto 0);
signal tx_data_6_reg  : std_logic_vector(7 downto 0);
signal tx_data_7_reg  : std_logic_vector(7 downto 0);
signal tx_data_8_reg  : std_logic_vector(7 downto 0);
signal tx_data_9_reg  : std_logic_vector(7 downto 0);
signal tx_data_10_reg : std_logic_vector(7 downto 0);
signal tx_data_11_reg : std_logic_vector(7 downto 0);
signal tx_data_12_reg : std_logic_vector(7 downto 0);


signal reset_mode_reg       : std_logic;
signal extended_mode_reg    : std_logic;
signal rst_sync_sig         : std_logic;

begin

acceptance_code_0 <= acceptance_code_0_reg;
acceptance_code_1 <= acceptance_code_1_reg;
acceptance_code_2 <= acceptance_code_2_reg;
acceptance_code_3 <= acceptance_code_3_reg;
acceptance_mask_0 <= acceptance_mask_0_reg;
acceptance_mask_1 <= acceptance_mask_1_reg;
acceptance_mask_2 <= acceptance_mask_2_reg;
acceptance_mask_3 <= acceptance_mask_3_reg;
               
tx_data_0  <=     tx_data_0_reg ;
tx_data_1  <=     tx_data_1_reg ;
tx_data_2  <=     tx_data_2_reg ;
tx_data_3  <=     tx_data_3_reg ;
tx_data_4  <=     tx_data_4_reg ;
tx_data_5  <=     tx_data_5_reg ;
tx_data_6  <=     tx_data_6_reg ;
tx_data_7  <=     tx_data_7_reg ;
tx_data_8  <=     tx_data_8_reg ;
tx_data_9  <=     tx_data_9_reg ;
tx_data_10 <=     tx_data_10_reg;
tx_data_11 <=     tx_data_11_reg;
tx_data_12 <=     tx_data_12_reg;
                   

we_mode                  <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(0,8)) else '0';                  
we_command               <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(1,8)) else '0';                   
we_bus_timing_0          <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(6,8)) and reset_mode_reg = '1' else '0';     
we_bus_timing_1     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(7,8)) and reset_mode_reg = '1' else '0';
we_clock_divider_low<= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(31,8)) else '0';            
we_clock_divider_hi <= '1' when we_clock_divider_low = '1' and reset_mode_reg = '1' else '0';    

read <= '1' when cs = '1' and we = '0' else '0';

we_acceptance_code_0 <= '1' when cs = '1' and we = '1' and reset_mode_reg = '1' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(4,8) ) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(16,8))) else '0'; 
we_acceptance_mask_0 <= '1' when cs = '1' and we = '1' and reset_mode_reg = '1' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(5,8) ) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(20,8))) else '0'; 
we_tx_data_0         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(10,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(16,8))) else '0'; 
we_tx_data_1         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(11,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(17,8))) else '0'; 
we_tx_data_2         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(12,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(18,8))) else '0'; 
we_tx_data_3         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(13,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(19,8))) else '0'; 
we_tx_data_4         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(14,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(20,8))) else '0'; 
we_tx_data_5         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(15,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(21,8))) else '0'; 
we_tx_data_6         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(16,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(22,8))) else '0'; 
we_tx_data_7         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(17,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(23,8))) else '0'; 
we_tx_data_8         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(18,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(24,8))) else '0'; 
we_tx_data_9         <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  ((extended_mode_reg = '0' and addr = conv_std_logic_vector(19,8)) or (extended_mode_reg = '1' and addr = conv_std_logic_vector(25,8))) else '0'; 
we_tx_data_10        <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  (                                     extended_mode_reg = '1' and addr = conv_std_logic_vector(26,8)) else '0'; 
we_tx_data_11        <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  (                                     extended_mode_reg = '1' and addr = conv_std_logic_vector(27,8)) else '0'; 
we_tx_data_12        <= '1' when cs = '1' and we = '1' and reset_mode_reg = '0' and  (                                     extended_mode_reg = '1' and addr = conv_std_logic_vector(28,8)) else '0'; 


we_acceptance_code_1     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(17,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';
we_acceptance_code_2     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(18,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';
we_acceptance_code_3     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(19,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';
we_acceptance_mask_1     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(21,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';
we_acceptance_mask_2     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(22,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';
we_acceptance_mask_3     <= '1' when cs = '1' and we = '1' and (addr = conv_std_logic_vector(23,8)) and reset_mode_reg = '1' and extended_mode_reg = '1' else '0';


-- Mode register 

ODE_REG: can_register_asyn 
generic map
(  WIDTH       => 8
  ,RESET_VALUE => 1 -- 8-bit Reg Value ate Reset
)

port map
(  data_in  => data_in
  ,data_out => mode
  ,we       => we_mode
  ,clk      => clk
  ,rst      => rst
);

reset_mode             <= reset_mode_reg;
reset_mode_reg         <= mode(0);
listen_only_mode       <= mode(1);
acceptance_filter_mode <= mode(3);
sleep_mode             <= mode(4);

-- End Mode register 

-- Command register 

rst_sync_sig <= command(0) or command (1) or command (2) or command(3) or command(4);

COMMAND_REG: can_register_asyn_syn
generic map
( WIDTH       => 5
 ,RESET_VALUE => 0)
port map
(  data_in  => data_in(4 downto 0)
  ,data_out => command(4 downto 0)
  ,we       => we_command
  ,clk      => clk
  ,rst      => rst
  ,rst_sync => rst_sync_sig
);

 self_rx_request    <= command(4);
 clear_data_overrun <= command(3);
 release_buffer     <= command(2);
 abort_tx           <= command(1);
 tx_request         <= command(0);

-- End Command register 




-- Bus Timing 0 register 
BUS_TIMING_0_REG: can_register 
generic map
( WIDTH => 8)
port map 
(  data_in  => data_in
  ,data_out => bus_timing_0
  ,we       => we_bus_timing_0
  ,clk      => clk
);

baud_r_presc    <= bus_timing_0(5 downto 0);
sync_jump_width <= bus_timing_0(7 downto 6);

-- End Bus Timing 0 register 


-- Bus Timing 1 register 
BUS_TIMING_1_REG: can_register
generic map
( WIDTH => 8)
port map 
(  data_in  => data_in
  ,data_out => bus_timing_1
  ,we       => we_bus_timing_1
  ,clk      => clk
);

time_segment1   <= bus_timing_1(3 downto 0);
time_segment2   <= bus_timing_1(6 downto 4);
triple_sampling <= bus_timing_1(7);
-- End Bus Timing 1 register 


-- Clock Divider register 
CLOCK_DIVIDER_REG_HI: can_register
generic map
( WIDTH => 5)
port map 
(  data_in  => data_in(7 downto 3)
  ,data_out => clock_divider(7 downto 3)
  ,we       => we_clock_divider_hi
  ,clk      => clk
);

CLOCK_DIVIDER_REG_LOW: can_register 
generic map
( WIDTH => 3)
port map
(  data_in  => data_in(2 downto 0)
  ,data_out => clock_divider(2 downto 0)
  ,we       => we_clock_divider_low
  ,clk      => clk
);

extended_mode      <= extended_mode_reg;
extended_mode_reg  <= clock_divider(7);
rx_int_enable      <= clock_divider(5);
clock_off          <= clock_divider(3);
cd(2 downto 0)     <= clock_divider(2 downto 0);