?? os_cpu.h
字號(hào):
/*
*********************************************************************************************************
* uC/OS-II
* The Real-Time Kernel
*
* (c) Copyright 1992-1999, Jean J. Labrosse, Weston, FL
* All Rights Reserved
*
* M683xx Specific code
* SDS C V7.4
*
* File : OS_CPU.H
* By : Jean J. Labrosse
*********************************************************************************************************
*/
/*
*********************************************************************************************************
* REVISION HISTORY
*
* $Log: J:/software/ucos-ii/m683xx/sds/source/vc/os_cpu.h_v $
*
* Rev 1.3 01 May 1999 11:51:40 JJL
* ***************************** M683xx REL V1.05 ******************************
* - Added check of OSIntNesting in OSIntExit68K() (see OS_CPU_A.S).
*
* Rev 1.2 29 Jun 1999 22:04:02 JJL
* ***************************** M683xx REL V1.04 ******************************
* - Added function OSIntExit68K() (see OS_CPU_A.S) which must now be JUMPed to
* at the end of ALL ISRs. Your ISR code MUST now look as follows:
*
* _YourISR:
* ADDQ.B #1,_OSIntNesting ; OSIntNesting++
* MOVEM.L A0-A6/D0-D7,-(A7) ; Save ALL registers
* ; CLEAR the INTERRUPT source!
* JSR _YourISRHandler
* JMP _OSIntExit68K ; Exit through uC/OS-II at end of ISR
*
* As you can see, you MUST increment OSIntNesting at the beginning of the ISR
* and NOT call OSIntExit(). OSIntExit68K() knows to return to task level code
* because it examines the stack frame for the contents of the Status register
* (SR) that is pushed onto the stack when the CPU recognizes an interrupt.
*
* Rev 1.1 09 May 1999 11:06:56 JJL
* ***************************** M683xx REL V1.03 ******************************
* - The stack adjustment constant in OSIntCtxSw() was set incorrectly. The
* correct value needed to be 10 instead of 18 because the SDS compiler
* doesn't allocate local variables for OSIntExit().
*
* - The function OSSetVect() in OS_CPU_C.C didn't properly cast 'addr'. The
* correct statement is:
* *pvect = (INT32U)addr;
* instead of:
* *pvect = (INT32U *)addr;
*
* Rev 1.0 07 Feb 1999 21:25:32 JJL
* ***************************** M683xx REL V1.02 ******************************
* - Initial release of the SDS port for uC/OS-II. The revision number matches
* that of other M683xx or M680x0 ports.
*********************************************************************************************************
*/
/*$PAGE*/
/*
*********************************************************************************************************
* DATA TYPES
*********************************************************************************************************
*/
#ifndef _OS_CPU_H
#define _OS_CPU_H
typedef unsigned char BOOLEAN;
typedef unsigned char INT8U; /* Unsigned 8 bit quantity */
typedef signed char INT8S; /* Signed 8 bit quantity */
typedef unsigned short INT16U; /* Unsigned 16 bit quantity */
typedef signed short INT16S; /* Signed 16 bit quantity */
typedef unsigned int INT32U; /* Unsigned 32 bit quantity */
typedef signed int INT32S; /* Signed 32 bit quantity */
typedef float FP32; /* Single precision floating point */
typedef double FP64; /* Double precision floating point */
#define BYTE INT8S /* Define data types for backward compatibility ... */
#define UBYTE INT8U /* ... to uC/OS V1.xx */
#define WORD INT16S
#define UWORD INT16U
#define LONG INT32S
#define ULONG INT32U
typedef unsigned short OS_STK; /* Each stack entry is 16-bit wide */
/*
*********************************************************************************************************
* CONSTANTS
*********************************************************************************************************
*/
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#endif
/*
*********************************************************************************************************
* Motorola 683xx
*
* Method #1: Disable/Enable interrupts using simple instructions. After critical section, interrupts
* will be enabled even if they were disabled before entering the critical section.
*
* Method #2: Disable/Enable interrupts by preserving the state of interrupts. In other words, if
* interrupts were disabled before entering the critical section, they will be disabled when
* leaving the critical section.
*********************************************************************************************************
*/
#define OS_CRITICAL_METHOD 2
#if OS_CRITICAL_METHOD == 1
#define OS_ENTER_CRITICAL() asm(" ORI #$0700,SR\n")
#define OS_EXIT_CRITICAL() asm(" AND #$0F800,SR\n")
#endif
#if OS_CRITICAL_METHOD == 2
#define OS_ENTER_CRITICAL() asm(" MOVE SR,-(A7)\n ORI #$0700,SR\n")
#define OS_EXIT_CRITICAL() asm(" MOVE (A7)+,SR\n")
#endif
#define OS_TASK_SW() asm(" TRAP #15\n")
#define OS_STK_GROWTH 1 /* Define stack growth: 1 = Down, 0 = Up */
/*
*********************************************************************************************************
* Motorola 683xx
*********************************************************************************************************
*/
#define CPU_INT_DIS() _asm(" ORI #$0700,SR\n") /* Disable interrupts */
#define CPU_INT_EN() _asm(" AND #$0F800,SR\n") /* Enable interrupts */
#define OS_INITIAL_SR 0x2000 /* Supervisor mode, interrupts enabled */
#define OS_TRAP_NBR 15 /* OSCtxSw() invoked through TRAP #15 */
void OSVectSet(INT8U vect, void (*addr)(void));
void *OSVectGet(INT8U vect);
void OSIntExit68K(void);
#endif
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