#undef public
#ifdef __SC16C554__
#define public
#else
#define public extern
#endif


/***********************************************************************************************

                                      全局函數聲明

***********************************************************************************************/
public void C554RstEna(void);
public void C554RstDis(void);
public void C554RegInit(void);

public Byte C554ByteRd(Byte cCom,Byte cRegister);
public void C554ByteWr(Byte cCom, Byte cRegister,Byte cData);
public void SentOneData(Byte cPort, Byte cData);
public Byte ReceiveDataErrorCheck(Byte cPort);
public Byte TransmitBufferEmptyCheck(Byte cPort);


/***********************************************************************************************

                                      全局變量定義

***********************************************************************************************/
#if 0
/*錯誤標志變量，1：有錯誤，0：沒有錯誤*/
public Byte cC554RecErr;
  #define ERR_PORT_A 1  /*cC554RecErr.0*/
  #define ERR_PORT_B 2  /*cC554RecErr.1*/
  #define ERR_PORT_C 4  /*cC554RecErr.2*/
  #define ERR_PORT_D 8  /*cC554RecErr.3*/
#endif 

/*SC16C554的COM選擇ID,是acC554Com[4]的索引號*/
  #define PORT_A 0
  #define PORT_B 1
  #define PORT_C 2
  #define PORT_D 3  


#define COM_ALL_ENABLE	0x00
#define COM_A_ENABLE	0xE0	/*  P4.4 = 0 */	
#define COM_B_ENABLE	0xD0	/*  P4.5 = 0*/
#define COM_C_ENABLE	0xB0	/*  P4.6 = 0*/
#define COM_D_ENABLE	0x70	/*  P4.7 = 0*/		


/***********************************************************************************************

                                      MCU與SC16C554硬件連接定義

***********************************************************************************************/
  #define C554_OUTPUT_MODE()  { PM3 = 0;}
  #define C554_INPUT_MODE()   { PM3 = 0xFF;}

  #define P_C554_RESET P12.6
  #define C554_RESET_ENA() {P12.6 = 1;}
  #define C554_RESET_DIS()  {P12.6 = 0;}

  #define P_IOW P12.4
  #define P_IOR P12.5
  #define C554_DATA_BUS P3  
  #define P_RXRDY P12.3
  #define P_TXRDY P12.2

 /*P47至P41分別為CSD,CSC,CSB,CSA,ADDR2,ADDR1,ADDR0；P40用于其它地方*/
  #define C554_SELECT_PEND P4


  #define C554_WRITE_VALID  P_IOW=0  
  #define C554_WRITE_INVALID  P_IOW=1
  #define C554_READ_VALID P_IOR=0 
  #define C554_READ_INVALID P_IOR=1

  /*當C554的接收FIFO中至少有一個數據，RXRDY引腳為低電平*/
  #define C554_RECFIFO_VALID()  (P_RXRDY==0) 

  /*當C554的發送FIFO中沒有數據時，TXRDY引腳為低電平*/
  #define C554_TRANSMIT_END() (P_TXRDY==0) 

  #define C554_INTA  P0.1
  #define C554_INTB  P0.2
  #define C554_INTC  P0.3
  #define C554_INTD  P0.4

/***********************************************************************************************

                            SC16C554的寄存器相關設定

***********************************************************************************************/

  /*Write only Register*/
  /*當LCR[7]=0時，可以寫入的寄存器*/
  #define C554_THR  (0x00<<1) /*Transmit Holding Register */
  #define C554_FCR  (0x02<<1) /*FIFO Control Register*/

  /*Read only Register*/
  /*當LCR[7]=1時，可以寫入的寄存器*/
  #define C554_RHR  (0x00<<1) /*Receive Holding Register*/  
  #define C554_ISR  (0x02<<1) /*Interrupt Status Register*/
  #define C554_LSR  (0x05<<1) /*Line Status Register*/  
  #define C554_MSR  (0x06<<1) /*Modem Status Register*/

  /*Write/Read Register*/
  /*當LCR[7]=BF時，可以寫入的寄存器*/
  #define C554_IER  (0x01<<1) /*Interrupt Enable Register*/           
  #define C554_LCR  (0x03<<1) /*Line Control Register*/
  #define C554_MCR  (0x04<<1) /*Moden Control Register*/
  #define C554_SPR  (0x07<<1) /*ScratchPad Register*/    
  /*當LCR[7]=1時，可以寫入的寄存器*/
  #define C554_DLL  (0x00<<1) /*LSB of Divisor Latch*/
  #define C554_DLM  (0x01<<1) /*MSB of Divisor Latch*/
  /*Write/Read Register*/
  /*當LCR[7]=BF時，可以寫入的寄存器*/
  #define C554_EFR  (0x02<<1) /*Enhance Feature Register*/
  #define C554_Xon1 (0x04<<1) /*Xon1 Word*/
  #define C554_Xon2 (0x05<<1) /*Xon2 Word*/
  #define C554_Xoff1 (0x06<<1)  /*Xoff1 Word*/
  #define C554_Xoff2  (0x07<<1) /*Xoff2 Word*/



  /*以下為C554中寄存器的初始化設定值*/
  #define C554_INT_LSR 0x06 /*receive line status register*/
  #define C554_INT_REC_RDY 0x04 /*receive data ready*/
  #define C554_INT_REC_TMOUT 0x0C /*receive data time out*/
  #define C554_INT_TRANSMIT_EMPTY 0x02 /*transmit empty*/
  #define C554_INT_MSR 0 /*Modem status register*/
  #define C554_INT_REC_MATCH 0x10 /*receive Xoff signal*/

  #define C554_LCR_MD0_INIT 0x1A  /*EVEN parity, one stop bit, 7bit word length*/
  #define C554_LCR_MD1_INIT 0x9A  /*Divisor setting*/
  #define C554_LCR_MD2_INIT 0xBF  /*Enhance feature setting*/

  /*當LCR[7]=0時，可以寫入的寄存器*/
#if 0
//  #define C554_IER_INIT  0x00  /*All interruption disable*/
#else
  #define C554_IER_INIT 0x01  /* Enable the receiver ready interrupt*/ 
#endif

  #define C554_FCR_INIT 0x07  /*DMA mode 0,FIFO enable,Receive/transmit FIFO reset*/
//  #define C554_FCR_INIT 0x8F  /*trigger level 8 chars. DMA mode 1,FIFO enable,Receive/transmit FIFO reset*/

#if 0
  #define C554_MCR_INIT 0x00  /*modem related mode disable,all interrupt disable*/
#else
  #define C554_MCR_INIT 0x08  /*modem related mode disable,Received data interrupt Enable*/
#endif	

  #define C554_SPR_INIT 0x00  /*ScratchPad setting*/

  /*當LCR[7]=1時，可以寫入的寄存器*/
  #define C554_DLL_INIT 0x0C  /*OSC = 1.8432MHz BAUD = 9600 bit/s*/
  #define C554_DLM_INIT 0x00

  /*當LCR[7]=BF時，可以寫入的寄存器*/
  #define C554_EFR_INIT   0x00  /*Enhanced feature disable*/
//  #define C554_XON1_INIT  0x00  
//  #define C554_XON2_INIT  0x00
//  #define C554_XOFF1_INIT 0x00
//  #define C554_XOFF2_INIT 0x00


  /*C554的Interrupt priority status word的中斷優先級*/
  #define ISR_PRI1_RLSR 0x06 /*Receive Line Status Reg*/
  #define ISR_PRI2_RXRDY 0x04 /*Received Data Ready---RXRDY*/
  #define ISR_PRI2_RXTMOUT 0x0C /*Receive Data time-out---RXRDY*/
  #define ISR_PRI3_TXRDY 0x02 /*Transmitnter Holding Reg Empty---TXRDY*/
  #define ISR_PRI4_MSR 0x00 /*Modem Status Reg*/
  #define ISR_PRI5_RXXOFF 0x10 /*Receive Xoff signal---RXRDY*/
  #define ISR_PRI6_CRTS 0x20 /*CTS,RTS change of state*/

  #define LSR_DATA_ERROR 0x80 /*LSR[7]=1,At least one parity error,framing
            error or break indication in FIFO data,
            This bit is cleared whel lSR is read*/
  #define LSR_TRANSMIT_EMPTY 0x40 /*LSR[6]=1,the transmit FIFO and transimit
                Shifting Reg are both empty*/
  #define LSR_OVERRUN 0x02 /*LSR[1]=1, overrun error*/
  #define LSR_RFIFO_READY 0x01 /*LSR[0]=1,Data has been receive and is  
                  saved in the receive holding register or FIFO*/