LDR	r1, =INTEGRATOR_HDR_BASE	LDR	r2, [r1, #INTEGRATOR_HDR_OSC_OFFSET]	AND	r2, r2, #(3 << 23)	CMP	r2, #(1 << 23)	BNE	clock1#if defined(CPU_920T) || defined(CPU_920T_T) || \    defined(CPU_940T) || defined(CPU_940T_T)	/*	 * if HDR_OSC indicates (bits[23:24] = 01), set	 * implementation-specific bits in the MMU control register - set	 * asynchronous mode.	 */	MRC	CP_MMU, 0, r2, c1, c0, 0	ORR	r2, r2, #MMUCR_ASYNC	MCR	CP_MMU, 0, r2, c1, c0, 0#endifclock1:	/* If bits[23:24] were 0, set asynchronous mode in HDR_CTRL */	LDRLT	r2, [r1, #INTEGRATOR_HDR_CTRL_OFFSET]	BICLT	r2, r2, #INTEGRATOR_HDR_CTRL_FASTBUS	STRLT	r2, [r1, #INTEGRATOR_HDR_CTRL_OFFSET]	/*	 * setup default clocks	 *	 * Core clock must always be greater than memory clock.	 *	 * Read HDR_PROC register, if this is non zero then there is no	 * coprocessor, in this case use the default settings. First,	 * load the default settings.	 */	LDR	r2, =INTEGRATOR_HDR_OSC_DFLT_VAL	LDR	r1, =INTEGRATOR_HDR_BASE	LDR	r3, [r1, #INTEGRATOR_HDR_PROC_OFFSET]	CMP	r3, #0	BNE	write_clock		/*	 * HDR_PROC was zero => there is a coprocessor. Get the processor ID.	 *	 * If the processor type is not recognised then the default settings	 * will be used.	 *	 * For safety's sake, make the following conditional upon there being a	 * coprocessor in the CPU.	 */#if defined(CPU_720T)  || defined(CPU_720T_T)  || \    defined(CPU_740T)  || defined(CPU_740T_T)  || \    defined(CPU_920T)  || defined(CPU_920T_T)  || \    defined(CPU_940T)  || defined(CPU_940T_T)  || \    defined(CPU_946ES) || defined(CPU_946ES_T) || \    defined(CPU_966ES) || defined(CPU_966ES_T)	MRC	CP_MMU, 0, r1, c0, c0, 0	MOV	r3, r1, LSL #16	MOV	r3, r3, LSR #20		/* move bits 15-3 to 12-0 */	CMP	r3, #0x720		/* is this a 720 */	LDREQ	r2, =INTEGRATOR_HDR_OSC_720T_VAL	BEQ	write_clock	CMP	r3, #0x740		/* is this a 740 */        LDREQ   r2, =INTEGRATOR_HDR_OSC_740T_VAL	BEQ     write_clock	CMP	r3, #0x940		/* is this a 940 */	LDREQ	r2, =INTEGRATOR_HDR_OSC_940T_VAL	BEQ	write_clock	LDR	r12, =0x946	CMP	r3, r12			/* is this a 946ES */	LDREQ	r2, =INTEGRATOR_HDR_OSC_946ES_VAL	BEQ	write_clock	CMP	r3, #0x920		/* is this a 920 */	LDREQ	r2, =INTEGRATOR_HDR_OSC_920T_VAL	BEQ	write_clock	MOV	r1, r3, LSR #4		/* is this a 966 */	CMP	r1, #0x96	BNE	write_clock	AND	r1, r3, #0xF	CMP	r1, #6	LDREQ	r2, =INTEGRATOR_HDR_OSC_966ES_VAL#endif /* defined(CPU_720T/740T/920T/940T/966ES) */write_clock:	/* Write clock settings */	LDR	r1, =INTEGRATOR_HDR_BASE	LDR	r3, =0xA05F	STR	r3, [r1, #INTEGRATOR_HDR_LOCK_OFFSET]	STR	r2, [r1, #INTEGRATOR_HDR_OSC_OFFSET]	MOV	r2, #0	STR	r2, [r1, #INTEGRATOR_HDR_LOCK_OFFSET]	/* Set up System BUS and PCI clocks */	LDR	r1, =INTEGRATOR_SC_BASE	STR	r3, [r1, #INTEGRATOR_SC_LOCK_OFFSET]	LDR	r2, =(INTEGRATOR_SC_OSC_SYS_20MHz | INTEGRATOR_SC_OSC_PCI_33MHz)	STR	r2, [r1, #INTEGRATOR_SC_OSC_OFFSET]	MOV	r2, #0	STR	r2, [r1, #INTEGRATOR_SC_LOCK_OFFSET]	/* Initialize static memory. */	MOV	r1, #INTEGRATOR_EBI_BASE		/* CS0 - ROM (Boot Flash) */	MOV	r2, #INTEGRATOR_EBI_8_BIT | INTEGRATOR_EBI_WS_3	STR	r2, [r1, #INTEGRATOR_EBI_CSR0_OFFSET]	/* CS1 - Flash (Application Flash) */	MOV	r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WS_3	STR	r2, [r1, #INTEGRATOR_EBI_CSR1_OFFSET]	/* CS2 - SSRAM (Not on Rev A Boards) */	MOV	r2, #INTEGRATOR_EBI_32_BIT | INTEGRATOR_EBI_WRITE_ENABLE | \		     INTEGRATOR_EBI_SYNC | INTEGRATOR_EBI_WS_2	STR	r2, [r1, #INTEGRATOR_EBI_CSR2_OFFSET]	/* CS3 - Unused (Set up for debug) */	MOV	r2, #INTEGRATOR_EBI_8_BIT | INTEGRATOR_EBI_WRITE_ENABLE	STR	r2, [r1, #INTEGRATOR_EBI_CSR3_OFFSET]		/*	 * Initialize external target memory.	 * Copied (with modifications for GNU) from uHAL.	 *	 * Size SDRAM (see CM940T User Guide, ARM DUI0125A - s.4.3.8, p.4-16)	 *	 * Check to see if the SPD data has been loaded.  If the load has	 * not completed we will loop upto 64K times before giving up.	 */	LDR	r1, =INTEGRATOR_HDR_SDRAM	/* Load address of HDR_SDRAM */	MOV	r2, #0x10000			/* Load count */sdram1:	LDR	r3, [r1]			/* Load contents of HDR_SDRAM */	/* Check to see if SPD data is loaded */	TST	r3, #INTEGRATOR_HDR_SDRAM_SPD_OK	BNE	sdram2	SUBS	r2, r2, #1			/* Decrement the count */	B	sdram5sdram2:	/* Load address of the base of SPD data */	LDR	r1, =INTEGRATOR_HDR_SPDBASE	MOV	r3, #0	/* Calculate the memory size from the SPD data. */	LDRB	r2, [r1, #31]		/* Get Module Bank Density */	MOV	r2, r2, LSL #2		/* Multiply by 4 */	LDRB	r3, [r1, #5]		/* Get Number of Banks */	MULS	r2, r3, r2		/* Multiply to to get size in MBytes */	BEQ	sdram5			/* If zero then something's gone wrong*/	/* The maximum SDRAM DIMM supported is 256 Mbytes */	CMP	r2, #256	BGT	sdram5	/*	 * We need to convert the size in MBytes to the value the value	 * to write to the MEMSIZE field of HDR_SDRAM.  The formula to do	 * this is as follows -	 *	 * 	MEMSIZE = LOG2(SizeInMB) - 4	 *	 * All the sizes that are supported are powers of 2 so a simple	 * algorithm to find LOG2 of number is to count the number of trailing	 * zeros.	 */	MOV	r1, #0		/* Initialise the counter */sdram4:	TST	r2, #1		/* Is the bottom bit set of the size varible */	MOVEQ	r2, r2, LSR #1	/* If not set then divide by 2 */	ADDEQ	r1, r1, #1	/* If not set then increment the counter */	BEQ	sdram4		/* If not set then loop */	CMP	r2, #1		/* $w2 should now contain 1 */	BNE	sdram5		/* If it doesn't then something has gone wrong*/	/* Load base address of header registers */	LDR	r2, =INTEGRATOR_HDR_BASE	/* Load contents of HDR_SDRAM */	LDR	r3, [r2, #INTEGRATOR_HDR_SDRAM_OFFSET]	AND	r3, r3, #3	/* Clear the everything except CASLAT */	SUBS	r1, r1, #4	/* Subtract 4 from the number of trailing bits*/	BMI	sdram5 		/* If negative then something has gone wrong */	ORR	r3, r3, r1, LSL #2	/* Merge it into contents of HDR_SDRAM*/	LDRB	r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 3)] /* No. of Rows */	AND	r1, r1, #0xF		/* Only want bottom 4 bits */	ORR	r3, r3, r1, LSL #8	/* Merge into HDR_SDRAM */	LDRB	r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 4)] /* Num Columns */	AND	r1, r1, #0xF		/* Only want bottom 4 bits */	ORR	r3, r3, r1, LSL #12	/* Merge into HDR_SDRAM */	LDRB	r1, [r2, #(INTEGRATOR_HDR_SPDBASE_OFFSET + 5)] /* No. of Banks*/	AND	r1, r1, #0xF		/* Only want bottom 4 bits */	ORR	r3, r3, r1, LSL #16	/* Merge into HDR_SDRAM */	/* Write back to HDR_SDRAM */	STR	r3, [r2, #INTEGRATOR_HDR_SDRAM_OFFSET]	/*	 * Now calculate the size of memory in bytes, this is done by	 * shifting 1 by MEMSIZE + 24.  The magic number 24 is the 4 we	 * subtracted earlier plus 20 to get the value is bytes (2^20	 * being 1 Mbyte).	 */	MOV	r1, r3, LSR #2		/* Need to extract MEMSIZE from the */	AND	r1, r1, #0x7		/* value we wrote to HDR_SDRAM */	MOV	r2, #1			/* Load 1 */	ADD	r1, r1, #24		/* Add 24 to the MEMSIZE value */	MOV	r1, r2, LSL r1		/* Shift 1 by (24 + MEMSIZE) */	B	sdram6sdram5:	MOV	r1, #0			/* Could not find any good DRAM */	sdram6:	/* Load base address of header registers */	LDR	r2, =INTEGRATOR_HDR_BASE	/* Load contents of HDR_STAT */	LDR	r2, [r2, #INTEGRATOR_HDR_STAT_OFFSET]	/* Clear all but bits 23:16 to get SSRAM size */	ANDS	r2, r2, #0xFF0000	/* If zero then this is a old header with 256K */	MOVEQ	r2, #0x00040000	CMP	r1, r2		/* Is there less SDRAM than the SSRAM */	MOVMI	r1, r2		/* If so then return the size of the SSRAM */	/* r1 now contains memory size: store this in Memory_Size variable */	LDR	r3, L$_memSize	STR	r1, [r3]	MOV	r3, r1		/* Need to return size in both these registers*/		/*	 * End of DRAM initialisation.	 *	 * Initialize the stack pointer to just before where the	 * uncompress code, copied from ROM to RAM, will run.	 */	LDR	sp, L$_STACK_ADDR	MOV	fp, #0			/* zero frame pointer */	/* jump to C entry point in ROM: routine - entry point + ROM base */#if	(ARM_THUMB)	LDR	r12, L$_rStrtInRom	ORR	r12, r12, #1		/* force Thumb state */	BX	r12#else	LDR	pc, L$_rStrtInRom#endif	/* (ARM_THUMB) *//******************************************************************************//* * PC-relative-addressable pointers - LDR Rn,=sym is broken * note "_" after "$" to stop preprocessor performing substitution */	.balign	4L$_HiPosn:	.long	ROM_TEXT_ADRS + HiPosn - FUNC(romInit)L$_rStrtInRom:	.long	ROM_TEXT_ADRS + FUNC(romStart) - FUNC(romInit)L$_STACK_ADDR:	.long	STACK_ADRSL$_memSize:	.long	VAR(integratorMemSize)#if defined(CPU_940T) || defined (CPU_940T_T)L$_sysCacheUncachedAdrs:	.long	SYS_CACHE_UNCACHED_ADRS#endif /* defined(CPU_940T, CPU_940T_T) */