;/*-----------------------------------------------------------------------------
;@@@@
;@@@@ (Summary)	: Cache init program
;@@@@
;@@@@ (Comment)	: 
;@@@@
;@@@@ (Author)	:  
;@@@@
;@@@@ (History)	: Date 		Modifier	Comment
;@@@@
;@@@@ (RCS ID)	: $Header$
;@@@@
;-----------------------------------------------------------------------------*/
	GET CACHEip.h
	GET CACHEchip.h
	GET CACHEsystem.h

	MACRO
$label	APD_CACHE_SETTING

    LDR r0, =APD_CACHE_BASE;
;/********************************************************************
; Protection Unit(SegXStart, SegXSize, SegXCfg Register)
;********************************************************************
;***************************************
	; set CACHE Segment Start Registers 0-7 
    ;**************************************/
    LDR r1, =(APD_CACHE0_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE0_START_OFFSET];
    LDR r1, =(APD_CACHE1_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE1_START_OFFSET];
    LDR r1, =(APD_CACHE2_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE2_START_OFFSET];
    LDR r1, =(APD_CACHE3_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE3_START_OFFSET];
    LDR r1, =(APD_CACHE4_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE4_START_OFFSET];
    LDR r1, =(APD_CACHE5_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE5_START_OFFSET];
    LDR r1, =(APD_CACHE6_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE6_START_OFFSET];
    LDR r1, =(APD_CACHE7_START:AND:APD_CACHE_START_VALID)
    STR r1, [r0, #APD_CACHE7_START_OFFSET];

    ;/***************************************
	;set CACHE Segment Size Registers 0-7 
    ;***************************************/
    LDR r1, =(APD_CACHE0_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE0_SIZE_OFFSET];
    LDR r1, =(APD_CACHE1_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE1_SIZE_OFFSET];
    LDR r1, =(APD_CACHE2_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE2_SIZE_OFFSET];
    LDR r1, =(APD_CACHE3_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE3_SIZE_OFFSET];
    LDR r1, =(APD_CACHE4_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE4_SIZE_OFFSET];
    LDR r1, =(APD_CACHE5_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE5_SIZE_OFFSET];
    LDR r1, =(APD_CACHE6_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE6_SIZE_OFFSET];
    LDR r1, =(APD_CACHE7_SIZE:AND:APD_CACHE_SIZE_VALID)
    STR r1, [r0, #APD_CACHE7_SIZE_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 0 
    ;***************************************/
    IF ((APD_CACHE0_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE0_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE0_SP Error;
    ENDIF

    IF ((APD_CACHE0_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE0_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE0_UP Error;
    ENDIF

    IF ((APD_CACHE0_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE0_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE0_B Error;
    ENDIF

    IF ((APD_CACHE0_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE0_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE0_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE0_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE0_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE0_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE0_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE0_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 1 
    ;***************************************/
    IF ((APD_CACHE1_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE1_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE1_SP Error;
    ENDIF

    IF ((APD_CACHE1_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE1_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE1_UP Error;
    ENDIF

    IF ((APD_CACHE1_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE1_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE1_B Error;
    ENDIF

    IF ((APD_CACHE1_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE1_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE1_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE1_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE1_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE1_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE1_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE1_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 2 
    ;***************************************/
    IF ((APD_CACHE2_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE2_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE2_SP Error;
    ENDIF

    IF ((APD_CACHE2_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE2_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE2_UP Error;
    ENDIF

    IF ((APD_CACHE2_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE2_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE2_B Error;
    ENDIF

    IF ((APD_CACHE2_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE2_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE2_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE2_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE2_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE2_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE2_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE2_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 3 
    ;***************************************/
    IF ((APD_CACHE3_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE3_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE3_SP Error;
    ENDIF

    IF ((APD_CACHE3_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE3_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE3_UP Error;
    ENDIF

    IF ((APD_CACHE3_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE3_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE3_B Error;
    ENDIF

    IF ((APD_CACHE3_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE3_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE3_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE3_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE3_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE3_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE3_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE3_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 4 
    ;***************************************/
    IF ((APD_CACHE4_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE4_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE4_SP Error;
    ENDIF

    IF ((APD_CACHE4_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE4_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE4_UP Error;
    ENDIF

    IF ((APD_CACHE4_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE4_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE4_B Error;
    ENDIF

    IF ((APD_CACHE4_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE4_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE4_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE4_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE4_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE4_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE4_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE4_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 5 
    ;***************************************/
    IF ((APD_CACHE5_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE5_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE5_SP Error;
    ENDIF

    IF ((APD_CACHE5_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE5_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE5_UP Error;
    ENDIF

    IF ((APD_CACHE5_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE5_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE5_B Error;
    ENDIF

    IF ((APD_CACHE5_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE5_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE5_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE5_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE5_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE5_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE5_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE5_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 6 
    ;***************************************/
    IF ((APD_CACHE6_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE6_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE6_SP Error;
    ENDIF

    IF ((APD_CACHE6_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE6_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE6_UP Error;
    ENDIF

    IF ((APD_CACHE6_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE6_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE6_B Error;
    ENDIF

    IF ((APD_CACHE6_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE6_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE6_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE6_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE6_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE6_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE6_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE6_CFG_OFFSET];

    ;/***************************************
	;set CACHE Segment Config Registers 7 
    ;***************************************/
    IF ((APD_CACHE7_SP >= APD_CACHE_NO):LAND:\
        (APD_CACHE7_SP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE7_SP Error;
    ENDIF

    IF ((APD_CACHE7_UP >= APD_CACHE_NO):LAND:\
        (APD_CACHE7_UP <= APD_CACHE_READ_WRITE))
	ELSE
         APD_CACHE7_UP Error;
    ENDIF

    IF ((APD_CACHE7_B = APD_CACHE_NOT_BUFFERABLE):LOR:\
        (APD_CACHE7_B = APD_CACHE_BUFFERABLE))
	ELSE
         APD_CACHE7_B Error;
    ENDIF

    IF ((APD_CACHE7_C = APD_CACHE_NOT_CACHEABLE):LOR:\
        (APD_CACHE7_C = APD_CACHE_CACHEABLE))
	ELSE
         APD_CACHE7_C Error;
    ENDIF
 
    LDR r1, =((APD_CACHE7_SP:SHL:APD_CACHE_SP_OFFSET):OR:\
              (APD_CACHE7_UP:SHL:APD_CACHE_UP_OFFSET):OR:\
              (APD_CACHE7_B:SHL:APD_CACHE_B_OFFSET):OR:\
              (APD_CACHE7_C:SHL:APD_CACHE_C_OFFSET));
    STR r1, [r0, #APD_CACHE7_CFG_OFFSET];

    ;/***************************************
	;set CACHE Control Register 
    ;***************************************/
    IF ((APD_CACHE_L >= APD_CACHE_NO_LOCK):LAND:\
        (APD_CACHE_L <= APD_CACHE_LOCK_LINE_WRITE))
	ELSE
         APD_CACHE_L Error;
    ENDIF

    IF ((APD_CACHE_BE = APD_CACHE_LITTLE_ENDIAN):LOR:\
        (APD_CACHE_BE = APD_CACHE_BIG_ENDIAN))
	ELSE
         APD_CACHE_BE Error;
    ENDIF

    IF ((APD_CACHE_W = APD_CACHE_WB_DISABLE):LOR:\
        (APD_CACHE_W = APD_CACHE_WB_ENABLE))
	ELSE
         APD_CACHE_W Error;
    ENDIF

    IF ((APD_CACHE_CM = APD_CACHE_WRITE_BACK):LOR:\
        (APD_CACHE_CM = APD_CACHE_WRITE_THROUGH))
	ELSE
         APD_CACHE_CM Error;
    ENDIF



    IF ((APD_CACHE_SM = APD_CACHE_CACHE4KB):LOR:(APD_CACHE_SM = APD_CACHE_SRAM4KB))
	ELSE
         APD_CACHE_SM Error;
    ENDIF

	IF (APD_CACHE_SM = APD_CACHE_SRAM4KB)
	    LDR r1, =APD_CACHE_S_START
    	STR r1, [r0, #APD_CACHE_S_START_OFFSET];

		LDR r1, =((APD_CACHE_S_START:AND:APD_CACHE_MAIN_ADDR_VALID):OR:\
				  (APD_CACHE_ENABLE:SHL:APD_CACHE_MAIN_MODE_OFFSET):OR:\
				  (APD_CACHE_DISABLE:SHL:APD_CACHE_MAIN_E_OFFSET))
		LDR r2, =APD_CACHE_MAIN_ASB_CTL_OFFSET;
		STR r1, [r2];

		LDR r1, = APD_CACHE_L_V:OR:APD_CACHE_BE_V:OR:\
		          APD_CACHE_W_V:OR:APD_CACHE_CM_V:OR:\
		          APD_CACHE_CE_D:OR:APD_CACHE_SE_E:OR:\
		          APD_CACHE_F_V:OR:APD_CACHE_I_V:OR:\
		          APD_CACHE_SM_V
	    STR r1, [r0, #APD_CACHE_CONTROL_OFFSET];
	ENDIF
	
	IF (APD_CACHE_SM = APD_CACHE_CACHE4KB)
		LDR r1, = APD_CACHE_L_V:OR:APD_CACHE_BE_V:OR:\
		          APD_CACHE_W_V:OR:APD_CACHE_CM_V:OR:\
		          APD_CACHE_CE_E:OR:APD_CACHE_SE_D:OR:\
		          APD_CACHE_F_V:OR:APD_CACHE_I_V:OR:\
		          APD_CACHE_SM_V
	    STR r1, [r0, #APD_CACHE_CONTROL_OFFSET];

		LDR r1, =((APD_CACHE_DISABLE:SHL:APD_CACHE_MAIN_MODE_OFFSET):OR:\
				  (APD_CACHE_DISABLE:SHL:APD_CACHE_MAIN_E_OFFSET))
		LDR r2, =APD_CACHE_MAIN_ASB_CTL_OFFSET;
		STR r1, [r2];
	ENDIF

	MEND
	
	END