LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   K:\PRODEV\VSM\PIC12\eeprom\12ce67x.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  09/04/02
Modified: 05/07/06

*PROPERTIES,0    

*MODELDEFS,17   
8051 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH
AT89 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH
AVR : RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND
BSTAMP : RSHI=20, RSLO=20,RWHI=20k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS
CMOS : RHI=100,RLO=100,TRISE=1u,TFALL=1u,V+=VDD,V-=VSS
HC11 : RHI=20, RLO=20,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS
LPC2100 : RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=V3,V-=VSS
MSP430 : RSHI=20, RSLO=20,RWHI=100k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND
NMOS : RHI=100,RLO=10,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VCC,V-=GND
PIC : RSHI=20, RSLO=20,RWHI=20k,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,V+=VDD,V-=VSS
PLD : RHI=20,RLO=20, V+=VCC,V-=GND,FLOAT=HIGH
RS232 : VLO=-8.5,VHI=8.5,RHI=300,RLO=300,VTL=1.2,VHL=0.5,VTH=1.7,VHH=0.5,RPOS=5k,RNEG=5k,V+=VCC,V-=GND,FLOAT=HIGH
TTL : RHI=50, RLO=5,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,V+=VCC,V-=GND,FLOAT=HIGH
TTLHC : RHI=5,RLO=5, V+=VCC,V-=GND
TTLHCT : RHI=5,RLO=5, V+=VCC,V-=GND
TTLLS : RHI=100, RLO=10,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=12k,RNEG=50k, V+=VCC,V-=GND,FLOAT=HIGH
TTLS : RHI=25, RLO=2.5,VUD=2,VTL=0.8,VHL=0.2,VTH=2.5,VHH=0.2,RPOS=5k,RNEG=20k,TRISE=0.5n,TFALL=0.5n, V+=VCC,V-=GND,FLOAT=HIGH

*PARTLIST,10   
U1_#P,POWER,PIC,ADC_ACQUISITION_TIME=20u,ADC_RCCLOCK_PERIOD=4u,ADC_SAMPLE_DELAY=100n,CFGWORD=0x3F74,CLOCK=4MHz,DBG_ADC_BREAK=0,DBG_ADC_WARNINGS=0,DBG_ADDRESSES=0,DBG_DUMP_CFGWORD=0,DBG_GENERATE_CLKOUT=0,DBG_I2CMEM_LOG=0,DBG_I2CMEM_WARN=1,DBG_RANDOM_DMEM=1,DBG_RANDOM_PMEM=0,DBG_STACK=1,DBG_STARTUP_DELAY=0,DBG_UNIMPLEMENTED_MEMORY=1,DBG_UNIMPLEMENTED_OPCODES=1,DBG_WAKEUP_DELAY=0,MODDLL=PIC12C6.DLL,PACKAGE=DIL08,PORTTDHL=0,PORTTDLH=0,PRIMITIVE=POWER,PRIMTYPE=12673,PROGRAM=TEST1.HEX,WDT_PERIOD=18m
U1_CPU,PIC12C67X,PIC12C67X,ADC_ACQUISITION_TIME=20u,ADC_RCCLOCK_PERIOD=4u,ADC_SAMPLE_DELAY=100n,CFGWORD=0x3F74,CLOCK=4MHz,DBG_ADC_BREAK=0,DBG_GENERATE_CLKOUT=0,DBG_RANDOM_DMEM=1,DBG_RANDOM_PMEM=0,DBG_STARTUP_DELAY=0,DBG_WAKEUP_DELAY=0,MODDLL=PIC12C6.DLL,PORTTDHL=0,PORTTDLH=0,PRIMITIVE=DIGITAL,PRIMTYPE=12673,PROGRAM=TEST1.HEX,TRACE_ADC=1,TRACE_CORE=1,TRACE_INTERRUPT=1,TRACE_LOAD=1,TRACE_MEMORY=1,TRACE_RESET=1,TRACE_SETUP=1,TRACE_SLEEP=1,TRACE_TIMER0=1,TRACE_TIMER1=1,TRACE_WDT=1,WDT_PERIOD=18m
U1_EEPROM,EEPROM,EEPROM,ADDRWIDTH=4,ALWAYS_ACK_DATA=1,BLKADDRMASK=0x00,BLKADDRSHIFT=0,BYTETIMING=0,CMDWIDTH=8,DATAWIDTH=8,DVCADDRMASK=0x00,DVCADDRSHIFT=0,INCRADDR=0,MEMSIZE=16,MODDATA="16,255",MODDLL=I2CMEM.DLL,PRIMITIVE=DIGITAL,TD_BUSFREE=1.3u,TD_CLK_ACK=100n,TD_CLK_ENDDATA=100n,TD_CLK_HIGH=600n,TD_CLK_LOW=1.3u,TD_CLK_SDO=900n,TD_CLK_UNACK=100n,TD_DATA_SETUP=100n,TD_RSTART_SETUP=600n,TD_START_HOLD=600n,TD_STOP_SETUP=600n,TD_WP_HOLD=0,TD_WP_SETUP=0,TD_WRITE=1m,TRACE=1,WPAGESIZE=1,WPHIGH=0x0007,WPLOW=0x0000
U2_#P,POWER,TTL,INIT=0,PACKAGE=DIL24,PRIMITIVE=POWER
U2_U2,JK,JK,INVERT=K,PRIMITIVE=DIGITAL
U2_U3,SHIFTREG_8,SHIFTREG_8,ARESET=TRUE,INIT=0,INVERT="RESET,LOAD",PRIMITIVE=DIGITAL,TDHLCQ=20n,TDLHCQ=17n,TDRQ=23n,TGQ=?
7SEG-BCD#0002,RTDPROBE,,PRIMITIVE=DIGITAL
7SEG-BCD#0003,RTDPROBE,,PRIMITIVE=DIGITAL
G3CB3021A,DIGITAL!,INT,COUNT=1,HIDDENPROPS=TRUE,INIT=LOW,MANUALEDITS=FALSE,PRIMITIVE=PROBE,START=500m
M3CB3021A,VPROBE,INT,PRIMITIVE=PROBE

*NETLIST,23   
#00036,2
U1_EEPROM,IP,SCK
U1_CPU,OP,SCL

#00037,2
U1_EEPROM,IO,SDA
U1_CPU,IO,SDA

#U2#00046,2
U2_U2,PS,D
U2_U3,OP,QL

#U2#00047,2
U2_U2,PS,Q
U2_U3,IP,DL

#U2#00048,1
U2_U3,OP,QU

#U2#00049,1
U2_U3,IP,DU

#00000,1
U1_CPU,IO,GP5/OSC1

#00001,1
U1_CPU,IO,GP4/OSC2/AN3

#00005,3
U1_CPU,IO,GP2/T0CKI/INT/AN2
G3CB3021A,OP,*
M3CB3021A,IP,*

#00004,2
U2_U3,IP,CLK
U1_CPU,IO,GP1/AN1/VREF

Q0,3
Q0,LBL
U2_U3,OP,Q0
7SEG-BCD#0003,IP,D0

Q1,3
Q1,LBL
U2_U3,OP,Q1
7SEG-BCD#0003,IP,D1

Q2,3
Q2,LBL
U2_U3,OP,Q2
7SEG-BCD#0003,IP,D2

Q3,3
Q3,LBL
U2_U3,OP,Q3
7SEG-BCD#0003,IP,D3

Q4,3
Q4,LBL
U2_U3,OP,Q4
7SEG-BCD#0002,IP,D0

Q5,3
Q5,LBL
U2_U3,OP,Q5
7SEG-BCD#0002,IP,D1

Q6,3
Q6,LBL
U2_U3,OP,Q6
7SEG-BCD#0002,IP,D2

Q7,3
Q7,LBL
U2_U3,OP,Q7
7SEG-BCD#0002,IP,D3

#00003,3
U2_U2,PS,K
U2_U2,PS,J
U1_CPU,IO,GP0/AN0

VDD,3
VDD,PT
U1_#P,PP,V+
U1_CPU,PP,VDD

VSS,3
VSS,PT
U1_#P,PP,V-
U1_CPU,PP,VSS

VCC,15
VCC,PT
U2_#P,PP,V+
U2_U3,IP,UP
U2_U3,IP,OE
U2_U3,IP,RESET
U2_U3,IP,LOAD
U2_U3,IP,D7
U2_U3,IP,D6
U2_U3,IP,D5
U2_U3,IP,D4
U2_U3,IP,D3
U2_U3,IP,D2
U2_U3,IP,D1
U2_U3,IP,D0
U1_CPU,IO,GP3/$MCLR$

GND,3
GND,PT
U2_#P,PP,V-
U2_U3,IP,HOLD

*GATES,0