LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\MICROCONTROLLERS\MAXIM\MAX225.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  23/08/04
Modified: 23/08/04

*PROPERTIES,2    
TDRX=500n
TDTX=1u

*MODELDEFS,0    

*PARTLIST,20   
R1,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R2,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R3,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R4,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R5,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R6,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R7,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R8,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R9,RES,400k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R10,RES,5k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
U1,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U2,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U3,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U4,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>
U5,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U6,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U7,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U8,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U9,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDTX>,TDLHDQ=<TDTX>
U10,TRIBUFFER,TRIBUFFER,INVERT="Q,OE",PRIMITIVE=DIGITAL,TDHLDQ=<TDRX>,TDLHDQ=<TDRX>

*NETLIST,24   
R1IN,3
R1IN,IT
U1,IP,D
R1,PS,1

R1OUT,2
R1OUT,OT
U1,OP,Q

$ENR1$,7
$ENR1$,IT
$ENR2$,IT
U1,IP,OE
U2,IP,OE
U3,IP,OE
U4,IP,OE
U10,IP,OE

R2IN,3
R2IN,IT
U2,IP,D
R5,PS,1

R2OUT,2
R2OUT,OT
U2,OP,Q

R3IN,3
R3IN,IT
U3,IP,D
R6,PS,1

R3OUT,2
R3OUT,OT
U3,OP,Q

R4IN,3
R4IN,IT
U4,IP,D
R7,PS,1

R4OUT,2
R4OUT,OT
U4,OP,Q

GND,6
GND,PR
R1,PS,2
R5,PS,2
R6,PS,2
R7,PS,2
R10,PS,2

T1IN,3
T1IN,IT
U5,IP,D
R2,PS,2

T1OUT,2
T1OUT,OT
U5,OP,Q

$ENT$,6
$ENT$,IT
U5,IP,OE
U6,IP,OE
U7,IP,OE
U8,IP,OE
U9,IP,OE

T2IN,3
T2IN,IT
U6,IP,D
R3,PS,2

T2OUT,2
T2OUT,OT
U6,OP,Q

T3IN,3
T3IN,IT
U7,IP,D
R4,PS,2

T3OUT,2
T3OUT,OT
U7,OP,Q

VCC,6
VCC,PR
R2,PS,1
R3,PS,1
R4,PS,1
R8,PS,1
R9,PS,1

T4IN,3
T4IN,IT
U8,IP,D
R8,PS,2

T4OUT,2
T4OUT,OT
U8,OP,Q

T5IN,3
T5IN,IT
U9,IP,D
R9,PS,2

T5OUT1,3
T5OUT1,OT
T5OUT2,OT
U9,OP,Q

R5IN,3
R5IN,IT
U10,IP,D
R10,PS,1

R5OUT,2
R5OUT,OT
U10,OP,Q

*GATES,0