LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\MICROCONTROLLERS\MAXIM\RS232\MAX250_251.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  24/08/04
Modified: 24/08/04

*PROPERTIES,0    

*MODELDEFS,0    

*PARTLIST,22   
G412AD212,VDC!,13.50,HIDDENPROPS=TRUE,MANUALEDITS=FALSE,PRIMITIVE=PROBE
M412AD212,VPROBE,SW1(A),PRIMITIVE=PROBE
R1,RES,220k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R2,RES,220k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R3,RES,220k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
R4,RES,220k,PRIMITIVE=DIGITAL,PRIMTYPE=RESISTOR
SW1,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1T,RON=1,TSWITCH=1u
SW2,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=1T,RON=1,TSWITCH=1u
U1,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U2,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U3,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U4,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U5,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U6,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U7,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U8,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U9,NAND_2,NAND_2,PRIMITIVE=DIGITAL
U10,NAND_2,NAND_2,PRIMITIVE=DIGITAL
U11,NAND_2,NAND_2,PRIMITIVE=DIGITAL
U12,NAND_2,NAND_2,PRIMITIVE=DIGITAL
U13,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U14,INVERTER,INVERTER,PRIMITIVE=DIGITAL

*NETLIST,23   
#00000,2
U2,IP,D
U6,OP,Q

#00001,5
U2,IP,OE
U1,IP,OE
U4,IP,OE
U3,IP,OE
U13,OP,Q

#00002,2
U3,IP,D
U8,OP,Q

#00003,2
U4,IP,D
U7,OP,Q

#00004,2
U1,IP,D
U5,OP,Q

#00005,2
U5,IP,D
U12,OP,Q

#00006,2
U6,IP,D
U11,OP,Q

#00007,2
U7,IP,D
U9,OP,Q

#00008,2
U8,IP,D
U10,OP,Q

#00009,11
U9,IP,D1
U10,IP,D1
U11,IP,D1
U12,IP,D1
U14,OP,Q
SW2,IP,EN
SW1,IP,EN
R3,PS,2
R4,PS,2
R1,PS,2
R2,PS,2

#00010,4
SW1,IO,A
SW2,IO,A
G412AD212,OP,*
M412AD212,IP,*

T2LDR,2
T2LDR,OT
U2,TS,Q

R2OUT,2
R2OUT,OT
U3,TS,Q

R1OUT,2
R1OUT,OT
U4,TS,Q

T1LDR,2
T1LDR,OT
U1,TS,Q

R1DIN,3
R1DIN,IT
U9,IP,D0
R2,PS,1

R2DIN,3
R2DIN,IT
U10,IP,D0
R1,PS,1

T2IN,3
T2IN,IT
U11,IP,D0
R4,PS,1

T1IN,3
T1IN,IT
U12,IP,D0
R3,PS,1

$EN$,2
$EN$,IT
U13,IP,D

SHDN,2
SHDN,IT
U14,IP,D

D1,2
D1,GT
SW1,IO,B

D2,2
D2,GT
SW2,IO,B

*GATES,0