LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\CMOS SERIES MODEL DESIGNS\4029\4029.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  07/06/03
Modified: 14/02/04

*PROPERTIES,1    
TGQ=?

*MAPPINGS,3,VALUE+VOLTAGE
4029+5V : TDLHDQ=200n, TDHLDQ=200n, TPHL=700n, TPLH=700n, TPZH=400n, TPLZ=400n, TGQ=?
4029+10V : TDLHDQ=100n, TDHLDQ=100n, TPHL=240n, TPLH=240n, TPZH=160n, TPLZ=160n, TGQ=?
4029+15V : TDLHDQ=50n, TDHLDQ=50n, TPHL=120n, TPLH=120n, TPZH=80n, TPLZ=80n, TGQ=?

*MODELDEFS,0    

*PARTLIST,6    
U1,COUNTER_4,COUNTER_4,ALOAD=1,ARESET=0,PRIMITIVE=DIGITAL,USEDIR=0
U2,NOR_2,NOR_2,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>
U3,OR_2,OR_2,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>
U4,AND_2,AND_2,INVERT=D0,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>
U5,AND_2,AND_2,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>
U6,AND_3,AND_3,INVERT=D2,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>

*NETLIST,22   
#00000,3
U1,IP,UCLK
U1,IP,DCLK
U5,OP,Q

#00001,2
U1,IP,RESET
U6,OP,Q

#00002,2
U1,OP,MIN
U3,IP,D1

#00003,2
U1,OP,MAX
U3,IP,D0

#00004,1
U1,OP,RCO

#00005,2
U2,OP,Q
U5,IP,D1

#00006,2
U3,OP,Q
U4,IP,D1

A,2
A,IT
U1,IP,D0

B,2
B,IT
U1,IP,D1

C,2
C,IT
U1,IP,D2

D,2
D,IT
U1,IP,D3

QA,3
QA,OT
U1,OP,Q0
U6,IP,D1

QB,2
QB,OT
U1,OP,Q1

QC,2
QC,OT
U1,OP,Q2

QD,3
QD,OT
U1,OP,Q3
U6,IP,D0

VDD,3
VDD,PR
U1,IP,OE
U1,IP,CE

PE,3
PE,IT
U1,IP,LOAD
U2,IP,D0

U/$D$,2
U/$D$,IT
U1,IP,CNTUP

CLK,2
CLK,IT
U5,IP,D0

CI,3
CI,IT
U2,IP,D1
U4,IP,D0

CO,2
CO,OT
U4,OP,Q

B/$D$,2
B/$D$,IT
U6,IP,D2

*GATES,0