/* * MPC8xx Communication Processor Module. * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) * * This file contains structures and information for the communication * processor channels.  Some CPM control and status is available * throught the MPC8xx internal memory map.  See immap.h for details. * This file only contains what I need for the moment, not the total * CPM capabilities.  I (or someone else) will add definitions as they * are needed.  -- Dan * * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 * bytes of the DP RAM and relocates the I2C parameter area to the * IDMA1 space.  The remaining DP RAM is available for buffer descriptors * or other use. */#ifndef __CPM_8XX__#define __CPM_8XX__#include <linux/config.h>#include <asm/8xx_immap.h>/* CPM Command register.*/#define CPM_CR_RST	((ushort)0x8000)#define CPM_CR_OPCODE	((ushort)0x0f00)#define CPM_CR_CHAN	((ushort)0x00f0)#define CPM_CR_FLG	((ushort)0x0001)/* Some commands (there are more...later)*/#define CPM_CR_INIT_TRX		((ushort)0x0000)#define CPM_CR_INIT_RX		((ushort)0x0001)#define CPM_CR_INIT_TX		((ushort)0x0002)#define CPM_CR_HUNT_MODE	((ushort)0x0003)#define CPM_CR_STOP_TX		((ushort)0x0004)#define CPM_CR_RESTART_TX	((ushort)0x0006)#define CPM_CR_CLOSE_RX_BD	((ushort)0x0007)#define CPM_CR_SET_GADDR	((ushort)0x0008)#define CPM_CR_SET_TIMER	CPM_CR_SET_GADDR/* Channel numbers.*/#define CPM_CR_CH_SCC1		((ushort)0x0000)#define CPM_CR_CH_I2C		((ushort)0x0001)	/* I2C and IDMA1 */#define CPM_CR_CH_SCC2		((ushort)0x0004)#define CPM_CR_CH_SPI		((ushort)0x0005)	/* SPI / IDMA2 / Timers */#define CPM_CR_CH_TIMER		CPM_CR_CH_SPI#define CPM_CR_CH_SCC3		((ushort)0x0008)#define CPM_CR_CH_SMC1		((ushort)0x0009)	/* SMC1 / DSP1 */#define CPM_CR_CH_SCC4		((ushort)0x000c)#define CPM_CR_CH_SMC2		((ushort)0x000d)	/* SMC2 / DSP2 */#define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))/* The dual ported RAM is multi-functional.  Some areas can be (and are * being) used for microcode.  There is an area that can only be used * as data ram for buffer descriptors, which is all we use right now. * Currently the first 512 and last 256 bytes are used for microcode. */#define CPM_DATAONLY_BASE	((uint)0x0800)#define CPM_DATAONLY_SIZE	((uint)0x0700)#define CPM_DP_NOSPACE		((uint)0x7fffffff)/* Export the base address of the communication processor registers * and dual port ram. */extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */uint		m8xx_cpm_dpalloc(uint size);uint		m8xx_cpm_hostalloc(uint size);void		m8xx_cpm_setbrg(uint brg, uint rate);/* Buffer descriptors used by many of the CPM protocols.*/typedef struct cpm_buf_desc {	ushort	cbd_sc;		/* Status and Control */	ushort	cbd_datlen;	/* Data length in buffer */	uint	cbd_bufaddr;	/* Buffer address in host memory */} cbd_t;#define BD_SC_EMPTY	((ushort)0x8000)	/* Receive is empty */#define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */#define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */#define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */#define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */#define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */#define BD_SC_CM	((ushort)0x0200)	/* Continous mode */#define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */#define BD_SC_P		((ushort)0x0100)	/* xmt preamble */#define BD_SC_BR	((ushort)0x0020)	/* Break received */#define BD_SC_FR	((ushort)0x0010)	/* Framing error */#define BD_SC_PR	((ushort)0x0008)	/* Parity error */#define BD_SC_NAK	((ushort)0x0004)	/* NAK - did not respond */#define BD_SC_OV	((ushort)0x0002)	/* Overrun */#define BD_SC_UN	((ushort)0x0002)	/* Underrun */#define BD_SC_CD	((ushort)0x0001)	/* ?? */#define BD_SC_CL	((ushort)0x0001)	/* Collision *//* Parameter RAM offsets.*/#define PROFF_SCC1	((uint)0x0000)#define PROFF_IIC	((uint)0x0080)#define PROFF_SCC2	((uint)0x0100)#define PROFF_SPI	((uint)0x0180)#define PROFF_SCC3	((uint)0x0200)#define PROFF_SMC1	((uint)0x0280)#define PROFF_SCC4	((uint)0x0300)#define PROFF_SMC2	((uint)0x0380)/* Define enough so I can at least use the serial port as a UART. * The MBX uses SMC1 as the host serial port. */typedef struct smc_uart {	ushort	smc_rbase;	/* Rx Buffer descriptor base address */	ushort	smc_tbase;	/* Tx Buffer descriptor base address */	u_char	smc_rfcr;	/* Rx function code */	u_char	smc_tfcr;	/* Tx function code */	ushort	smc_mrblr;	/* Max receive buffer length */	uint	smc_rstate;	/* Internal */	uint	smc_idp;	/* Internal */	ushort	smc_rbptr;	/* Internal */	ushort	smc_ibc;	/* Internal */	uint	smc_rxtmp;	/* Internal */	uint	smc_tstate;	/* Internal */	uint	smc_tdp;	/* Internal */	ushort	smc_tbptr;	/* Internal */	ushort	smc_tbc;	/* Internal */	uint	smc_txtmp;	/* Internal */	ushort	smc_maxidl;	/* Maximum idle characters */	ushort	smc_tmpidl;	/* Temporary idle counter */	ushort	smc_brklen;	/* Last received break length */	ushort	smc_brkec;	/* rcv'd break condition counter */	ushort	smc_brkcr;	/* xmt break count register */	ushort	smc_rmask;	/* Temporary bit mask */} smc_uart_t;/* Function code bits.*/#define SMC_EB	((u_char)0x10)	/* Set big endian byte order *//* SMC uart mode register.*/#define	SMCMR_REN	((ushort)0x0001)#define SMCMR_TEN	((ushort)0x0002)#define SMCMR_DM	((ushort)0x000c)#define SMCMR_SM_GCI	((ushort)0x0000)#define SMCMR_SM_UART	((ushort)0x0020)#define SMCMR_SM_TRANS	((ushort)0x0030)#define SMCMR_SM_MASK	((ushort)0x0030)#define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */#define SMCMR_REVD	SMCMR_PM_EVEN#define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */#define SMCMR_BS	SMCMR_PEN#define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */#define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */#define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)/* SMC2 as Centronics parallel printer.  It is half duplex, in that * it can only receive or transmit.  The parameter ram values for * each direction are either unique or properly overlap, so we can * include them in one structure. */typedef struct smc_centronics {	ushort	scent_rbase;	ushort	scent_tbase;	u_char	scent_cfcr;	u_char	scent_smask;	ushort	scent_mrblr;	uint	scent_rstate;	uint	scent_r_ptr;	ushort	scent_rbptr;	ushort	scent_r_cnt;	uint	scent_rtemp;	uint	scent_tstate;	uint	scent_t_ptr;	ushort	scent_tbptr;	ushort	scent_t_cnt;	uint	scent_ttemp;	ushort	scent_max_sl;	ushort	scent_sl_cnt;	ushort	scent_character1;	ushort	scent_character2;	ushort	scent_character3;	ushort	scent_character4;	ushort	scent_character5;	ushort	scent_character6;	ushort	scent_character7;	ushort	scent_character8;	ushort	scent_rccm;	ushort	scent_rccr;} smc_cent_t;/* Centronics Status Mask Register.*/#define SMC_CENT_F	((u_char)0x08)#define SMC_CENT_PE	((u_char)0x04)#define SMC_CENT_S	((u_char)0x02)/* SMC Event and Mask register.*/#define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */#define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */#define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */#define	SMCM_BSY	((unsigned char)0x04)#define	SMCM_TX		((unsigned char)0x02)#define	SMCM_RX		((unsigned char)0x01)/* Baud rate generators.*/#define CPM_BRG_RST		((uint)0x00020000)#define CPM_BRG_EN		((uint)0x00010000)#define CPM_BRG_EXTC_INT	((uint)0x00000000)#define CPM_BRG_EXTC_CLK2	((uint)0x00004000)#define CPM_BRG_EXTC_CLK6	((uint)0x00008000)#define CPM_BRG_ATB		((uint)0x00002000)#define CPM_BRG_CD_MASK		((uint)0x00001ffe)#define CPM_BRG_DIV16		((uint)0x00000001)/* SI Clock Route Register*/#define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)#define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)#define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)#define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)#define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)#define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)#define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)#define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)/* SCCs.*/#define SCC_GSMRH_IRP		((uint)0x00040000)#define SCC_GSMRH_GDE		((uint)0x00010000)#define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)#define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)#define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)#define SCC_GSMRH_REVD		((uint)0x00002000)#define SCC_GSMRH_TRX		((uint)0x00001000)#define SCC_GSMRH_TTX		((uint)0x00000800)#define SCC_GSMRH_CDP		((uint)0x00000400)#define SCC_GSMRH_CTSP		((uint)0x00000200)#define SCC_GSMRH_CDS		((uint)0x00000100)#define SCC_GSMRH_CTSS		((uint)0x00000080)#define SCC_GSMRH_TFL		((uint)0x00000040)#define SCC_GSMRH_RFW		((uint)0x00000020)#define SCC_GSMRH_TXSY		((uint)0x00000010)#define SCC_GSMRH_SYNL16	((uint)0x0000000c)#define SCC_GSMRH_SYNL8		((uint)0x00000008)#define SCC_GSMRH_SYNL4		((uint)0x00000004)#define SCC_GSMRH_RTSM		((uint)0x00000002)#define SCC_GSMRH_RSYN		((uint)0x00000001)#define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */#define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)#define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)#define SCC_GSMRL_EDGE_POS	((uint)0x20000000)#define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)#define SCC_GSMRL_TCI		((uint)0x10000000)#define SCC_GSMRL_TSNC_3	((uint)0x0c000000)#define SCC_GSMRL_TSNC_4	((uint)0x08000000)#define SCC_GSMRL_TSNC_14	((uint)0x04000000)#define SCC_GSMRL_TSNC_INF	((uint)0x00000000)#define SCC_GSMRL_RINV		((uint)0x02000000)#define SCC_GSMRL_TINV		((uint)0x01000000)#define SCC_GSMRL_TPL_128	((uint)0x00c00000)#define SCC_GSMRL_TPL_64	((uint)0x00a00000)#define SCC_GSMRL_TPL_48	((uint)0x00800000)#define SCC_GSMRL_TPL_32	((uint)0x00600000)#define SCC_GSMRL_TPL_16	((uint)0x00400000)#define SCC_GSMRL_TPL_8		((uint)0x00200000)#define SCC_GSMRL_TPL_NONE	((uint)0x00000000)#define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)#define SCC_GSMRL_TPP_01	((uint)0x00100000)#define SCC_GSMRL_TPP_10	((uint)0x00080000)#define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)#define SCC_GSMRL_TEND		((uint)0x00040000)#define SCC_GSMRL_TDCR_32	((uint)0x00030000)#define SCC_GSMRL_TDCR_16	((uint)0x00020000)#define SCC_GSMRL_TDCR_8	((uint)0x00010000)#define SCC_GSMRL_TDCR_1	((uint)0x00000000)#define SCC_GSMRL_RDCR_32	((uint)0x0000c000)#define SCC_GSMRL_RDCR_16	((uint)0x00008000)#define SCC_GSMRL_RDCR_8	((uint)0x00004000)#define SCC_GSMRL_RDCR_1	((uint)0x00000000)#define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)#define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)#define SCC_GSMRL_RENC_FM0	((uint)0x00001000)#define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)#define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)#define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)#define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)#define SCC_GSMRL_TENC_FM0	((uint)0x00000200)#define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)#define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)#define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */#define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)#define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)#define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)#define SCC_GSMRL_ENR		((uint)0x00000020)#define SCC_GSMRL_ENT		((uint)0x00000010)#define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)#define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)#define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)#define SCC_GSMRL_MODE_V14	((uint)0x00000007)#define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)#define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)#define SCC_GSMRL_MODE_UART	((uint)0x00000004)#define SCC_GSMRL_MODE_SS7	((uint)0x00000003)#define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)#define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)#define SCC_TODR_TOD		((ushort)0x8000)/* SCC Event and Mask register.*/#define	SCCM_TXE	((unsigned char)0x10)#define	SCCM_BSY	((unsigned char)0x04)#define	SCCM_TX		((unsigned char)0x02)#define	SCCM_RX		((unsigned char)0x01)typedef struct scc_param {	ushort	scc_rbase;	/* Rx Buffer descriptor base address */	ushort	scc_tbase;	/* Tx Buffer descriptor base address */	u_char	scc_rfcr;	/* Rx function code */	u_char	scc_tfcr;	/* Tx function code */	ushort	scc_mrblr;	/* Max receive buffer length */	uint	scc_rstate;	/* Internal */	uint	scc_idp;	/* Internal */	ushort	scc_rbptr;	/* Internal */	ushort	scc_ibc;	/* Internal */	uint	scc_rxtmp;	/* Internal */	uint	scc_tstate;	/* Internal */	uint	scc_tdp;	/* Internal */	ushort	scc_tbptr;	/* Internal */	ushort	scc_tbc;	/* Internal */	uint	scc_txtmp;	/* Internal */	uint	scc_rcrc;	/* Internal */	uint	scc_tcrc;	/* Internal */} sccp_t;/* Function code bits.