------------------------------------------------------------------------------  This file is a part of the GRLIB VHDL IP LIBRARY--  Copyright (C) 2004 GAISLER RESEARCH----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  See the file COPYING for the full details of the license.--------------------------------------------------------------------------------- Entity: 	mem_umc-- File:	mem_umc.vhd-- Author:	Jiri Gaisler - Gaisler Research-- Description:	UMC specific ram generators------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;package mem_umc is  component rhumc_syncram  generic ( abits : integer := 10; dbits : integer := 8 );  port (    clk      : in std_ulogic;    address  : in std_logic_vector(abits -1 downto 0);    datain   : in std_logic_vector(dbits -1 downto 0);    dataout  : out std_logic_vector(dbits -1 downto 0);    enable   : in std_ulogic;    write    : in std_ulogic);  end component;end;