------------------------------------------------------------------------------  This file is a part of the GRLIB VHDL IP LIBRARY--  Copyright (C) 2004 GAISLER RESEARCH----  This program is free software; you can redistribute it and/or modify--  it under the terms of the GNU General Public License as published by--  the Free Software Foundation; either version 2 of the License, or--  (at your option) any later version.----  See the file COPYING for the full details of the license.--------------------------------------------------------------------------------- Package: 	pads-- File:	pads.vhd-- Author:	Jiri Gaisler - Gaisler Research-- Description:	Tech-selection pads declaration------------------------------------------------------------------------------library ieee;use ieee.std_logic_1164.all;library grlib;use grlib.tech.all;package pads iscomponent inpad   generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v);  port (pad : in std_ulogic; o : out std_ulogic);end component; component inpadv   generic (tech : integer := 0; level : integer := 0; 	   voltage : integer := x33v; width : integer := 1);  port (    pad : in  std_logic_vector(width-1 downto 0);     o   : out std_logic_vector(width-1 downto 0));end component; component iopad   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	   voltage : integer := x33v; strength : integer := 12; 	   oepol : integer := 0);  port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);end component;component iopadv   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := x33v; strength : integer := 12; width : integer := 1; 	   oepol : integer := 0);  port (    pad : inout std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0);    en  : in  std_ulogic;    o   : out std_logic_vector(width-1 downto 0));end component;component iopadvv is  generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := 0; strength : integer := 0; width : integer := 1;	oepol : integer := 0);  port (    pad : inout std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0);    en  : in  std_logic_vector(width-1 downto 0);    o   : out std_logic_vector(width-1 downto 0));end component; component iodpad   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	   voltage : integer := x33v; strength : integer := 12; 	   oepol : integer := 0);  port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);end component;component iodpadv   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := x33v; strength : integer := 12; width : integer := 1; 	   oepol : integer := 0);  port (    pad : inout std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0);    o   : out std_logic_vector(width-1 downto 0));end component;component outpad   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	   voltage : integer := x33v; strength : integer := 12);  port (pad : out std_ulogic; i : in std_ulogic);end component;component outpadv   generic (tech : integer := 0; level : integer := 0; slew : integer := 0; 	   voltage : integer := x33v; strength : integer := 12; width : integer := 1);  port (    pad : out std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0));end component; component odpad   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	   voltage : integer := x33v; strength : integer := 12; 	   oepol : integer := 0);  port (pad : out std_ulogic; i : in std_ulogic);end component;component odpadv   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := x33v; strength : integer := 12; width : integer := 1; 	   oepol : integer := 0);  port (    pad : out std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0));end component; component toutpad   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	   voltage : integer := x33v; strength : integer := 12; 	   oepol : integer := 0);  port (pad : out std_ulogic; i, en : in std_ulogic);end component;component toutpadv   generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := x33v; strength : integer := 12; width : integer := 1; 	   oepol : integer := 0);  port (    pad : out std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0);    en  : in  std_ulogic);end component;component toutpadvv is  generic (tech : integer := 0; level : integer := 0; slew : integer := 0;	voltage : integer := 0; strength : integer := 0; width : integer := 1;	oepol : integer := 0);  port (    pad : out std_logic_vector(width-1 downto 0);     i   : in  std_logic_vector(width-1 downto 0);    en  : in  std_logic_vector(width-1 downto 0));end component;component clkpad   generic (tech : integer := 0; level : integer := 0; 	   voltage : integer := x33v; arch : integer := 0);  port (pad : in std_ulogic; o : out std_ulogic);end component; end;