library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library WORK;
use WORK.FOM_PKG.all;
entity E_CRC is
port (
Din: instd_logic;
CLK: instd_logic;
SMF_last: instd_logic;
CRC: outstd_logic_vector(3 downto 0)
);
end E_CRC;
architecture Behavior of E_CRC is
signalCRC_load:std_logic:=Low;
signalCRC_rst:std_logic:=Low;
signalat:std_logic:=Low;
signalbt:std_logic:=Low;
signalDF:std_logic_vector(3 downto 0):=(others=>'0');
begin
process(CLK)
begin
if CLK = Low and CLK'event then
CRC_load <= SMF_last;
end if;
end process;
process(CLK)
begin
if CLK = High and CLK'event then
CRC_rst <= CRC_load;
end if;
end process;

process (CLK,CRC_rst)-- CRC-4 Procedure
begin
if CLK = Low and CLK'event then  
if CRC_rst='1' then
DF<="0000";
else
DF(0)<=DF(1);
DF(1)<=DF(2);
DF(2)<=bt;
DF(3)<=at;
end if;
end if;
end process;
at<=Din XOR DF(0);
bt<=DF(3) XOR at;
process(CLK,CRC_load)
begin
if CLK = High and CLK'event then
if CRC_load = High then 
CRC <= DF;
--else
--CRC <= CRC;
end if;
end if;
end process;
end Behavior;
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