;**************************************
; Processor specific definitions

ep2DmaBuff:			equ	E8h
ep2DmaBuff0:			equ	ep2DmaBuff+0
ep2DmaBuff1:			equ	ep2DmaBuff+1
ep2DmaBuff2:			equ	ep2DmaBuff+2
ep2DmaBuff3:			equ	ep2DmaBuff+3
ep2DmaBuff4:			equ	ep2DmaBuff+4
ep2DmaBuff5:			equ	ep2DmaBuff+5
ep2DmaBuff6:			equ	ep2DmaBuff+6
ep2DmaBuff7:			equ	ep2DmaBuff+7

ep1DmaBuff: 			equ	F0h
ep1DmaBuff0:			equ	ep1DmaBuff+0
ep1DmaBuff1:			equ	ep1DmaBuff+1
ep1DmaBuff2:			equ	ep1DmaBuff+2
ep1DmaBuff3:			equ	ep1DmaBuff+3
ep1DmaBuff4:			equ	ep1DmaBuff+4
ep1DmaBuff5:			equ	ep1DmaBuff+5
ep1DmaBuff6:			equ	ep1DmaBuff+6
ep1DmaBuff7:			equ	ep1DmaBuff+7

ep0DmaBuff:			equ	F8h
ep0DmaBuff0:			equ	ep0DmaBuff+0
ep0DmaBuff1:			equ	ep0DmaBuff+1
ep0DmaBuff2:			equ	ep0DmaBuff+2
ep0DmaBuff3:			equ	ep0DmaBuff+3
ep0DmaBuff4:			equ	ep0DmaBuff+4
ep0DmaBuff5:			equ	ep0DmaBuff+5
ep0DmaBuff6:			equ	ep0DmaBuff+6
ep0DmaBuff7:			equ	ep0DmaBuff+7



;**************************************
; register definitions

PORT0: 				equ	00h ; GPIO data port 0
PORT1: 				equ	01h ; GPIO data port 1
PORT2: 				equ	02h ; GPIO data port 2
	SCLK: 			equ	20h
	DPLUS:			equ	20h
	SDATA:			equ	10h
	DMINUS:			equ	10h
	XTALIN:			equ	02h
	VREG:  			equ	01h

PORT0_INT:     			equ	04h ; Interrupt enable for Port 0
PORT1_INT:     			equ	05h ; Interrupt enable for Port 1
PORT0_INT_POLARITY: 		equ	06h ; Interrupt polarity for Port 0
PORT1_INT_POLARITY: 		equ	07h ; Interrupt polarity for Port 1

PORT0_MODE0:	    		equ	0Ah ; Mode Configuration 0 for Port 0
PORT0_MODE1:	    		equ	0Bh ; Mode Configuration 1 for Port 0
PORT1_MODE0:	    		equ	0Ch ; Mode Configuration 0 for Port 1
PORT1_MODE1:	    		equ	0Dh ; Mode Configuration 1 for Port 1

USB_ADDRESS:	    		equ	10h ; USB device address
	ADDRESS_ENABLE:		equ	80h
	ADDRESS_MASK:		equ	7Fh

EP0_COUNT:	    		equ	11h	; Endpoint 0 counter
	DATA_TOGGLE:		equ	80h
	DATA_VALID: 		equ	40h
	BYTE_COUNT: 		equ	0Fh

EP0_MODE:	    		equ	12h ; Endpoint 0 configuration
	EP0_SETUP:		equ	80h
	EP0_IN:	  		equ	40h
	EP0_OUT:  		equ	20h
	EP0_ACK:  		equ	10h
	MODE_MASK:		equ	0Fh

EP1_COUNT: 			equ	13h ; Endpoint 1 counter
EP1_MODE:  			equ	14h ; Endpoint 1 configuration
EP2_COUNT: 			equ	15h ; Endpoint 2 counter

EP2_MODE:  			equ	16h ; Endpoint 2 configuration
	EP_STALL: 		equ	80h
	EP_ACK:	  		equ	10h

USB_STATUS_CONTROL_REG:		equ	1Fh ; USB upstream status and control
	PS2_PULLUP:		equ	80h
	VREG_ENABLE:		equ	40h
	USB_PS2_MODE:		equ	20h
	BUS_ACTIVITY:		equ	08h
	CONTROL2:		equ	04h
	CONTROL1:		equ	02h
	CONTROL0:		equ	01h

	NOT_FORCING:		equ	00h
	FORCE_K:		equ	01h
	FORCE_J:		equ	02h
	FORCE_SE0:		equ	03h
	FORCEBOTH_LOW:		equ	04h
	FORCESDATA_LOW:		equ	05h
	FORCESCLK_LOW:		equ	06h
	FORCE_HIZ:		equ	07h

GLOBAL_INTERRUPT_REG:			equ	20h ; Global interrupt enable
	WAKEUP_INT:		equ	80h
	GPIO_INT:		equ	40h
	CAPTUREB_INT:		equ	20h
	CAPTUREA_INT:		equ	10h
	SPI_INT:		equ	08h
	1MS_INT:		equ	04h
	128US_INT:		equ	02h
	USB_RESET_INT:		equ	01h

ENDPOINT_INT:			equ	21h ; USB endpoint interrupt enable
	EP2_INT:		equ	04h
	EP1_INT:		equ	02h
	EP0_INT:		equ	01h

TIMER_LSB:			equ	24h ; Lower eight bits of timer
TIMER_MSB:			equ	25h ; Upper six bits of timer
WATCHDOG_REG:			equ	26h ; Clear watchdog Timer

CAPTUREA_RISING:		equ	40h ; Capture timer A rising register
CAPTUREA_FALLING:		equ	41h ; Capture timer A falling register
CAPTUREB_RISING:		equ	42h ; Capture timer B rising register
CAPTUREB_FALLING:		equ	43h ; Capture timer B falling register

CAPTURE_CONFIG:			equ	44h ; Capture timer configuration register
	FIRST_EDGE_HOLD:	equ	80h
	PRESCALE:		equ	70h
	PRESCALE2:		equ	40h
	PRESCALE1:		equ	20h
	PRESCALE0:		equ	10h
	CAPTUREB_FALL_INT:	equ	08h
	CAPTUREB_RISE_INT:	equ	04h
	CAPTUREA_FALL_INT:	equ	02h
	CAPTUREA_RISE_INT:	equ	01h

CAPTURE_STATUS:			equ	45h ; Capture timer status register
	CAPTUREB_FALL_EVENT:	equ	08h
	CAPTUREB_RISE_EVENT:	equ	04h
	CAPTUREA_FALL_EVENT:	equ	02h
	CAPTUREA_RISE_EVENT:	equ	01h

SPI_DATA:			equ	60h	; SPI data register

SPI_CONTROL:			equ	61h	; SPI configuration register
	TCMP:			equ	80h
	TBF:			equ	40h
	MODE1:			equ	20h
	MODE0:			equ	10h
	CPOL:			equ 	08h
	CPHA:			equ 	04h
	SCK_SELECT1:		equ 	02h
	SCK_SELECT0:		equ	01h	

CLOCK_CONFIG: 		        equ	F8h ; Internal/external oscillator configuration
	EXT_DELAY: 	        equ	80h
	WAKEUP_ADJUST2:		equ	40h
	WAKEUP_ADJUST1:		equ	20h
	WAKEUP_ADJUST0:		equ	10h
	LVR_DISABLE:		equ	08h
	PRECISION_USB_CLOCKING:	equ	04h
	INTERNAL_CLK:		equ	02h
	EXTERNAL_CLK:		equ	01h

CONTROL:			equ	FFh ; Processor status and control
	IRQ_PENDING:		equ	80h
	WATCHDOG_RESET:		equ	40h
	USB_RESET:		equ	20h
	POWERON_RESET:		equ	10h
	SUSPEND:		equ	08h
	INTERRUPT_MASK:		equ	04h
	SINGLE_STEP:		equ	02h
	RUN:			equ	01h


;**************************************
; USB mode encoding

DISABLE:			equ	00h
NAK_IN_OUT:			equ	01h
STATUS_OUT_ONLY:		equ	02h
STALL_IN_OUT:			equ	03h
IGNORE_IN_OUT:			equ	04h
ISOCHRONOUS_OUT:		equ	05h
STATUS_IN_ONLY:			equ	06h
ISOCHRONOUS_IN:			equ	07h
NAK_OUT:			equ	08h
ACK_OUT:			equ	09h
NAK_OUT_STATUS_IN:		equ	0Ah
ACK_OUT_NAK_IN:			equ	0Bh
NAK_IN:				equ	0Ch
ACK_IN:				equ	0Dh
NAK_IN_STATUS_OUT:		equ	0Eh
ACK_IN_STATUS_OUT:		equ	0Fh


;**************************************
; general use constants

SET:				equ	FFh
CLEAR:				equ	00h