module mem(addr, read, data);
input[5:0] addr;
input read;
output [7:0]data;
reg [7:0]memory[63:0];
assign data=(read)?memory[addr]:8'bzzzzzzzz; 

initial
	begin 	memory[0]=8'b00000100;
			memory[1]=8'b01000101;
			memory[2]=8'b11000000;
			memory[3]=8'b10000000;
			memory[4]=8'b00100111;
			memory[5]=8'b00111001;
			//other  memory cells not defeined

				
	end

endmodule