;------------------------------------------------------------------------
; MACRO.INC
;------------------------------------------------------------------------
; System MACRO definitions
;------------------------------------------------------------------------

;-------------------------------------------------------------------------
; JGE ( Greater than or Equal )
; if ACC >= Value, Jump to Addr
;-------------------------------------------------------------------------
MACRO   JGE Value, Addr
	CMP	    A, Value
	JNC	    Addr		
ENDM

;-------------------------------------------------------------------------
; JLT ( Less than )
; if ACC < Value, Jump to Addr
;-------------------------------------------------------------------------
MACRO   JLT Value, Addr
	CMP	    A, Value
	JC	    Addr		
ENDM

;-------------------------------------------------------------------------
; JNE ( Not Equal )
; if ACC != Value, Jump to Addr
;-------------------------------------------------------------------------
MACRO   JNE Value, Addr
	CMP	    A, Value
	JNZ	    Addr		
ENDM

;-------------------------------------------------------------------------
; JEQ ( Equal )
; if ACC == Value, Jump to Addr
;-------------------------------------------------------------------------
MACRO   JEQ Value, Addr
	CMP	    A, Value
	JZ	    Addr		
ENDM

;------------------------------------------------------------------------
; LD ( Load )
; Store the value to RAM variable through ACC.
; Caution: This macro is using ACC. ACC will be changed.
; example:    LD    Addr, Value
;------------------------------------------------------------------------
MACRO   LD  Addr, Value
    MOV     A, Value                
    MOV     [Addr], A
ENDM

;------------------------------------------------------------------------
; write
; I/O output (register) macro
; example:    write     DATA, REG_PORT_0        writes DATA to REG_PORT_0
; Ensure A = DATA on exit (may be used after MACRO call)
;------------------------------------------------------------------------
 MACRO   write  data, dest
    MOV     A, data
    IOWR    dest
 ENDM
;------------------------------------------------------------------------
; write_A
; I/O output (register) macro
; example:    write_A   REG_PORT_0              writes reg A to REG_PORT_0
;------------------------------------------------------------------------
 MACRO   write_A  dest
    IOWR    dest
 ENDM
;------------------------------------------------------------------------
; read
; I/O input (register) macro
; example:      read    REG_PORT_0              reads REG_PORT_0 to Acc
;------------------------------------------------------------------------
 MACRO  read    src
    IORD    src
 ENDM
;------------------------------------------------------------------------
; set_flag
; Set a system flag (set ONLY by an interrupt)
; example:    set_flag     flag         sets flag=1
;------------------------------------------------------------------------
 MACRO set_flag flag
    MOV     A, 01h
    MOV     [flag], A
 ENDM
;------------------------------------------------------------------------
; clr_flag
; Clear a system flag (cleared ONLY by a NON interrupt thread)
; example:    clr_flag     flag         clears flag=0
;------------------------------------------------------------------------
 MACRO clr_flag flag
    MOV     A, 0
    MOV     [flag], A
 ENDM
;------------------------------------------------------------------------
; test_flag
; Tests a system flag
; example:  test_flag     flag
; return:   ZF=1 if set
;------------------------------------------------------------------------
 MACRO test_flag flag
    MOV     A, [flag]
    XOR     A, 01h                      ; XOR faster than CMP
 ENDM
;------------------------------------------------------------------------
; test_state
; Tests a state
; example:  test_state    state, mask
; return:   ZF=1 if state=mask
;------------------------------------------------------------------------
 MACRO test_state state, mask
    MOV     A, [state]
    XOR     A, mask                     ; XOR faster than CMP
 ENDM
;------------------------------------------------------------------------
; feed_dog
; Watchdog timer reset
;------------------------------------------------------------------------
 MACRO  feed_dog
    IOWR    REG_WDT_CLEAR
 ENDM
;------------------------------------------------------------------------
; suspend
; Places CPU in "suspend and wait for interrupts" state (power reduction)
;------------------------------------------------------------------------
 MACRO  suspend
    read    REG_PROC_STAT               ; read processor status
    OR      A, MASK_SUSPEND             ; set the suspend bit
    write_A REG_PROC_STAT               ; save processor status
    NOP                                 ; PC+1 wakeup address
 ENDM
;------------------------------------------------------------------------
; unlock
; (Endpoint 0 MODE and any endpoint COUNT register specific unlock macro)
; Both Endpoint Mode and Count registers may be locked by the SIE on
; write attempts. A read will unlock the register if not locked but a wait
; for register availability for writes must be performed.
;------------------------------------------------------------------------
 MACRO unlock register, data
    IORD    register                    ; unlock Mode register
unlock_loop:
    MOV     A, data
    IOWR    register
    IORD    register                    ; confirm write was not locked
    CMP     A, data
    JNZ     unlock_loop
 ENDM
;------------------------------------------------------------------------
; unlock_EP
; (Endpoint 1 and 2 specific unlock macro for MODE registers)
; Similar to 'unlock' except TOKEN bits are always TRUE (1)
; Endpoint Mode registers may be locked by the SIE on write attempts.
; A read will unlock the register if not locked but a wait for register
; availability for writes must be performed.
;------------------------------------------------------------------------
 MACRO unlock_EP register, mode
    IORD    register                    ; unlock Mode register
unlock_EP_loop:
    MOV     A, mode
    IOWR    register
    IORD    register                    ; confirm write was not locked
    AND     A, MASK_MODE                ; Mask all but MODE bits
    CMP     A, mode
    JNZ     unlock_EP_loop
 ENDM
;------------------------------------------------------------------------
; enable_1ms_timer
;------------------------------------------------------------------------
 MACRO  enable_1ms_timer
    IORD    REG_GLOBAL_INT_ENABLE
    OR      A, MASK_1024US
    IOWR    REG_GLOBAL_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; disable_1ms_timer
;------------------------------------------------------------------------
 MACRO  disable_1ms_timer
    IORD    REG_GLOBAL_INT_ENABLE
    AND     A, ~MASK_1024US
    IOWR    REG_GLOBAL_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; enable_hub_address
; Enables USB address for SIE's response to this address
;------------------------------------------------------------------------
 MACRO enable_hub_address
    MOV     A, ~MASK_ADDRESS
    write_A REG_B_ADDRESS               ; clear device address, enable SIE
 ENDM
;------------------------------------------------------------------------
; enable_hub_int
;------------------------------------------------------------------------
 MACRO  enable_hub_int
    IORD    REG_GLOBAL_INT_ENABLE
    OR      A, MASK_HUB
    IOWR    REG_GLOBAL_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; disable_hub_int
;------------------------------------------------------------------------
 MACRO  disable_hub_int
    IORD    REG_GLOBAL_INT_ENABLE
    AND     A, ~MASK_HUB
    IOWR    REG_GLOBAL_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; enable_hub_ep0_int
;------------------------------------------------------------------------
 MACRO  enable_hub_ep0_int
    IORD    REG_EP_INT_ENABLE           ; enable the HUB EP0 interrupt
    OR      A, MASK_EPB0
    IOWR    REG_EP_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; disable_hub_ep0_int
;------------------------------------------------------------------------
 MACRO  disable_hub_ep0_int
    IORD    REG_EP_INT_ENABLE
    AND     A, ~MASK_EPB0
    IOWR    REG_EP_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; enable_hub_ep1_int
;------------------------------------------------------------------------
 MACRO  enable_hub_ep1_int
    IORD    REG_EP_INT_ENABLE           ; enable the HUB EP1 interrupt
    OR      A, MASK_EPB1
    IOWR    REG_EP_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; disable_hub_ep1_int
;------------------------------------------------------------------------
 MACRO  disable_hub_ep1_int
    IORD    REG_EP_INT_ENABLE
    AND     A, ~MASK_EPB1
    IOWR    REG_EP_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; enable_128us_timer
;------------------------------------------------------------------------
 MACRO  enable_128us_timer
    IORD    REG_GLOBAL_INT_ENABLE
    OR      A, MASK_128US
    IOWR    REG_GLOBAL_INT_ENABLE
 ENDM
;------------------------------------------------------------------------
; disable_128us_timer
;------------------------------------------------------------------------