/************************************************************************ * *      sead.h * *      The 'SEAD' module defines the SEAD board specific *      address-MAP, registers, etc. * * * ###################################################################### * * mips_start_of_legal_notice *  * Copyright (c) 2004 MIPS Technologies, Inc. All rights reserved. * * * Unpublished rights (if any) reserved under the copyright laws of the * United States of America and other countries. * * This code is proprietary to MIPS Technologies, Inc. ("MIPS * Technologies"). Any copying, reproducing, modifying or use of this code * (in whole or in part) that is not expressly permitted in writing by MIPS * Technologies or an authorized third party is strictly prohibited. At a * minimum, this code is protected under unfair competition and copyright * laws. Violations thereof may result in criminal penalties and fines. * * MIPS Technologies reserves the right to change this code to improve * function, design or otherwise. MIPS Technologies does not assume any * liability arising out of the application or use of this code, or of any * error or omission in such code. Any warranties, whether express, * statutory, implied or otherwise, including but not limited to the implied * warranties of merchantability or fitness for a particular purpose, are * excluded. Except as expressly provided in any written license agreement * from MIPS Technologies or an authorized third party, the furnishing of * this code does not give recipient any license to any intellectual * property rights, including any patent rights, that cover this code. * * This code shall not be exported, reexported, transferred, or released, * directly or indirectly, in violation of the law of any country or * international law, regulation, treaty, Executive Order, statute, * amendments or supplements thereto. Should a conflict arise regarding the * export, reexport, transfer, or release of this code, the laws of the * United States of America shall be the governing law. * * This code constitutes one or more of the following: commercial computer * software, commercial computer software documentation or other commercial * items. If the user of this code, or any related documentation of any * kind, including related technical data or manuals, is an agency, * department, or other entity of the United States government * ("Government"), the use, duplication, reproduction, release, * modification, disclosure, or transfer of this code, or any related * documentation of any kind, is restricted in accordance with Federal * Acquisition Regulation 12.212 for civilian agencies and Defense Federal * Acquisition Regulation Supplement 227.7202 for military agencies. The use * of this code by the Government is further restricted in accordance with * the terms of the license agreement(s) and/or applicable contract terms * and conditions covering this code from MIPS Technologies or an authorized * third party. * * * *  * mips_end_of_legal_notice *  * ************************************************************************/#ifndef SEAD_H#define  SEAD_H/************************************************************************ *  Note: all addresses are physical ! *  Must be mapped into kseg0 (system RAM) or kseg1 (registers, devices)*************************************************************************//************************************************************************ *  Include files ************************************************************************/#include "sysdefs.h"#include <msc01_memmap.h>#include <msc01_biu.h>#include <msc01_ic.h>#include <msc01_pbc.h>#include <msc01_mc.h>/************************************************************************ *  Definitions ************************************************************************//* The following mapping matches the msc01_system1 testbench used in * the SOC-it deliverables.  In this testbench, the IP blocks are attached * to the kernel as follows: * *   IP1:  "Testbench Monitor", not used in a real system *   IP2:  AHB bridge, PCI bridge, or nothing, depending on testbench build *   IP3:  Peripheral bus bridge. * * This configuration is reflected by the defines below: */#define MSC01_AHB_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP2)#define MSC01_PCI_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP2)#define MSC01_PBC_REG_BASE	MSC01_REGADDR(MSC01_REGSPACE_IP3)/************************************************************************ ************************************************************************ *  SEAD physical address MAP (512 MByte) ************************************************************************ ************************************************************************/#define  SEAD_SYSTEMRAM_BASE         	0x00000000 /* System RAM:     */#define  SEAD_SYSTEMRAM_SIZE         	0x10000000 /*   256 MByte     */#define  SEAD_RESERVED1_BASE         	0x10000000 /* Reserved:       */#define  SEAD_RESERVED1_SIZE         	0x0B000000 /*   176 MByte     */#define  SEAD_SD_BASE       	  	0x1B000000 /* SDRAM control:  */#define  SEAD_SD_SIZE       	  	0x00100000 /*     1 MByte     */#define  SEAD_GP_BASE              	0x1B100000 /* GPIO module:    */#define  SEAD_GP_SIZE              	0x00100000 /*     1 MByte     */#define  SEAD_PF_BASE                	0x1B200000 /* PF module:      */#define  SEAD_PF_SIZE                	0x00100000 /*     1 MByte     */#define  SEAD_RESERVED2_BASE         	0x1B300000 /* Reserved:       */#define  SEAD_RESERVED2_SIZE         	0x00D00000 /*    13 MByte     */#define  SEAD_SYSTEMFLASH_BASE       	0x1C000000 /* System Flash:   */#define  SEAD_SYSTEMFLASH_SIZE       	0x01FC0000 /*  31.75 MByte    */#define  SEAD_SYSTEMFLASH_SECTORSIZE 	0x00020000 /* Sect. = 128 KB  */#define  SEAD_SYSTEMFLASH_BANKCOUNT   	         2 /*                 */#define  SEAD_SYSTEMFLASH_BLOCKCOUNT   	        64 /*                 */#define  SEAD_FILEFLASH_BASE         	0x1DFC0000 /* File Flash:     */#define  SEAD_FILEFLASH_SIZE         	0x00040000 /*   256 KByte     */#define  SEAD_FILEFLASH_SECTORSIZE   	0x00020000 /* Sect. = 128 KB  */#define  SEAD_SRAM_BASE              	0x1E000000 /* System RAM:     */#define  SEAD_SRAM_SIZE              	0x00400000 /*     4 MByte     */#define  SEAD_RESERVED3_BASE         	0x1E400000 /* Reserved:       */#define  SEAD_RESERVED3_SIZE         	0x00400000 /*     4 MByte     */#define  SEAD_PI_BASE           	0x1E800000 /* PI-bus ctrl:    */#define  SEAD_PI_SIZE           	0x00400000 /*     4 MByte     */#define  SEAD_RESERVED4_BASE         	0x1EC00000 /* Reserved:       */#define  SEAD_RESERVED4_SIZE         	0x00400000 /*     4 MByte     */#define  SEAD_DEVICES_BASE           	0x1F000000 /* Devices:        */#define  SEAD_DEVICES_SIZE           	0x00C00000 /*    12 MByte     */#define  SEAD_BOOTPROM_BASE          	0x1FC00000 /* Boot PROM:      */#define  SEAD_BOOTPROM_SIZE          	0x00100000 /*     1 MByte     *//************************************************************************ *  SEAD, peripheral bus devices, base adresses: ************************************************************************/#define  SEAD_HDSP2532_BASE          	0x1F000400 /* ASCII display	*/#define  SEAD_TI16C550_DEV0_BASE     	0x1F000800 /* TI16C550 UART0	*/#define  SEAD_TI16C550_DEV1_BASE     	0x1F000900 /* TI16C550 UART1	*//************************************************************************ ************************************************************************ *  SEAD FPGA, PERIPHERAL REGISTERS: ************************************************************************ ************************************************************************//************************************************************************ *  REVISION: MUST BE FIXED TO  0x1FC00010 on any baseboard*************************************************************************//************************************************************************ *      Register Addresses*************************************************************************/#define SEAD_REVISION      	     	0x1FC00010 /* REVISION		*//************************************************************************ *      Register field encodings*************************************************************************//******** reg: REVISION ********//* field: RTLID */#define SEAD_REVISION_RTLID_SHF		26#define SEAD_REVISION_RTLID_MSK		(MSK(6) << SEAD_REVISION_RTLID_SHF)#define SEAD_REVISION_RTLID_BASIC	0x1#define SEAD_REVISION_RTLID_SOCIT101	0x2/* field: RTLMAJ */#define SEAD_REVISION_RTLMAJ_SHF	19#define SEAD_REVISION_RTLMAJ_MSK	(MSK(7) << SEAD_REVISION_RTLMAJ_SHF)/* field: RTLMIN */#define SEAD_REVISION_RTLMIN_SHF	12#define SEAD_REVISION_RTLMIN_MSK	(MSK(7) << SEAD_REVISION_RTLMIN_SHF)/* field: PROID */#define SEAD_REVISION_PROID_SHF		4#define SEAD_REVISION_PROID_MSK		(MSK(4) << SEAD_REVISION_PROID_SHF)/* field: PRORV */#define SEAD_REVISION_PRORV_SHF		0#define SEAD_REVISION_PRORV_MSK		(MSK(4) << SEAD_REVISION_PRORV_SHF)/************************************************************************ *  PERIPHERAL BUS SWITCHES (P-SWITCH):*************************************************************************//************************************************************************ *      P-SW Register Addresses*************************************************************************/#define SEAD_PSWITCH		   	0x1F000200 /* P-SWITCH         	*//************************************************************************ *      Register field encodings*************************************************************************//******** reg: PSWITCH ********//* bits 7:0: VAL */#define SEAD_PSWITCH_VAL_SHF	    	0#define SEAD_PSWITCH_VAL_MSK	    	(MSK(8) << SEAD_PSWITCH_VAL_SHF)/* bit 0: S3-1 */#define SEAD_PSWITCH_SW1_SHF	    	0#define SEAD_PSWITCH_SW1_MSK	    	(MSK(1) << SEAD_PSWITCH_SW1_SHF)#define SEAD_PSWITCH_SW1_ON           	SEAD_PSWITCH_SW1_MSK/* bit 1: S3-2 */#define SEAD_PSWITCH_SW2_SHF	    	1#define SEAD_PSWITCH_SW2_MSK	    	(MSK(1) << SEAD_PSWITCH_SW2_SHF)#define SEAD_PSWITCH_SW2_ON           	SEAD_PSWITCH_SW2_MSK/* bit 2: S3-3 */#define SEAD_PSWITCH_SW3_SHF	    	2#define SEAD_PSWITCH_SW3_MSK	    	(MSK(1) << SEAD_PSWITCH_SW3_SHF)#define SEAD_PSWITCH_SW3_ON           	SEAD_PSWITCH_SW3_MSK/* bit 3: S3-4 */#define SEAD_PSWITCH_SW4_SHF	    	3#define SEAD_PSWITCH_SW4_MSK	    	(MSK(1) << SEAD_PSWITCH_SW4_SHF)#define SEAD_PSWITCH_SW4_ON           	SEAD_PSWITCH_SW4_MSK/* bit 4: S3-5 */#define SEAD_PSWITCH_SW5_SHF	    	4#define SEAD_PSWITCH_SW5_MSK	    	(MSK(1) << SEAD_PSWITCH_SW5_SHF)#define SEAD_PSWITCH_SW5_ON           	SEAD_PSWITCH_SW5_MSK/* bit 5: S3-6 */#define SEAD_PSWITCH_SW6_SHF	    	5#define SEAD_PSWITCH_SW6_MSK	    	(MSK(1) << SEAD_PSWITCH_SW6_SHF)#define SEAD_PSWITCH_SW6_ON           	SEAD_PSWITCH_SW6_MSK/* bit 6: S3-7 */#define SEAD_PSWITCH_SW7_SHF	    	6#define SEAD_PSWITCH_SW7_MSK	  	(MSK(1) << SEAD_PSWITCH_SW7_SHF)#define SEAD_PSWITCH_SW7_ON           	SEAD_PSWITCH_SW7_MSK/* bit 7: S3-8 */#define SEAD_PSWITCH_SW8_SHF	    	7#define SEAD_PSWITCH_SW8_MSK	  	(MSK(1) << SEAD_PSWITCH_SW8_SHF)#define SEAD_PSWITCH_SW8_ON           	SEAD_PSWITCH_SW8_MSK/************************************************************************ *  PERIPHERAL BUS LEDs (P-LED):*************************************************************************//************************************************************************ *      P-LED Register Addresses*************************************************************************/#define SEAD_PLED		   	0x1F000210 /* P-LED         	*/