#endif#define	CONFIG_PCI#define	CONFIG_PCI_PNP#define	CFG_PCI_MSTR_IO_BUS	0x00000000	/* PCI base   */#if 1/* environment is in Flash */#define CFG_ENV_IS_IN_FLASH	1# define CFG_ENV_ADDR		(CFG_FLASH_BASE+0x30000)# define CFG_ENV_SIZE		0x10000# define CFG_ENV_SECT_SIZE	0x10000#else#define CFG_ENV_IS_IN_EEPROM	1#define CFG_ENV_OFFSET		0#define CFG_ENV_SIZE		2048#define CFG_EEPROM_PAGE_WRITE_BITS	4	/* 16-byte page size	*/#endif/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH*/#define BOOTFLAG_WARM		0x02	/* Software reboot                 *//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */#if (CONFIG_COMMANDS & CFG_CMD_KGDB)# define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */#endif/*----------------------------------------------------------------------- * HIDx - Hardware Implementation-dependent Registers                    2-11 *----------------------------------------------------------------------- * HID0 also contains cache control - initially enable both caches and * invalidate contents, then the final state leaves only the instruction * cache enabled. Note that Power-On and Hard reset invalidate the caches, * but Soft reset does not. * * HID1 has only read-only information - nothing to set. */#define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|\			 HID0_DCI|HID0_IFEM|HID0_ABE)#define CFG_HID0_FINAL  (HID0_IFEM|HID0_ABE)#define CFG_HID2        0/*----------------------------------------------------------------------- * RMR - Reset Mode Register                                     5-5 *----------------------------------------------------------------------- * turn on Checkstop Reset Enable */#define CFG_RMR         RMR_CSRE/*----------------------------------------------------------------------- * BCR - Bus Configuration                                       4-25 *----------------------------------------------------------------------- */#define BCR_APD01	0x10000000#define CFG_BCR		(BCR_APD01|BCR_ETM|BCR_LETM)	/* 8260 mode *//*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration                             4-31 *----------------------------------------------------------------------- */#define CFG_SIUMCR      (SIUMCR_BBD|SIUMCR_APPC10|\			 SIUMCR_CS10PC00|SIUMCR_BCTLC10)/*----------------------------------------------------------------------- * SYPCR - System Protection Control                             4-35 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\			 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)#else#define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\			 SYPCR_SWRI|SYPCR_SWP)#endif /* CONFIG_WATCHDOG *//*----------------------------------------------------------------------- * TMCNTSC - Time Counter Status and Control                     4-40 *----------------------------------------------------------------------- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, * and enable Time Counter */#define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control                 4-42 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable * Periodic timer */#define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)/*----------------------------------------------------------------------- * SCCR - System Clock Control                                   9-8 *----------------------------------------------------------------------- * Ensure DFBRG is Divide by 16 */#define CFG_SCCR        SCCR_DFBRG01/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration                         13-7 *----------------------------------------------------------------------- */#define CFG_RCCR        0#define CFG_MIN_AM_MASK	0xC0000000/*----------------------------------------------------------------------- * MPTPR - Memory Refresh Timer Prescaler Register              10-18 *----------------------------------------------------------------------- */#define CFG_MPTPR       0x1F00/*----------------------------------------------------------------------- * PSRT - Refresh Timer Register                                10-16 *----------------------------------------------------------------------- */#define CFG_PSRT        0x0f/*----------------------------------------------------------------------- * PSRT - SDRAM Mode Register                                   10-10 *----------------------------------------------------------------------- */	/* SDRAM initialization values for 8-column chips	 */#define CFG_OR2_8COL	(CFG_MIN_AM_MASK		|\			 ORxS_BPD_4			|\			 ORxS_ROWST_PBI1_A7		|\			 ORxS_NUMR_12)#define CFG_PSDMR_8COL	(PSDMR_PBI			|\			 PSDMR_SDAM_A15_IS_A5		|\			 PSDMR_BSMA_A15_A17		|\			 PSDMR_SDA10_PBI1_A7		|\			 PSDMR_RFRC_7_CLK		|\			 PSDMR_PRETOACT_3W		|\			 PSDMR_ACTTORW_2W		|\			 PSDMR_LDOTOPRE_1C		|\			 PSDMR_WRC_1C			|\			 PSDMR_CL_2)	/* SDRAM initialization values for 9-column chips	 */#define CFG_OR2_9COL	(CFG_MIN_AM_MASK		|\			 ORxS_BPD_4			|\			 ORxS_ROWST_PBI1_A6		|\			 ORxS_NUMR_12)#define CFG_PSDMR_9COL	(PSDMR_PBI			|\			 PSDMR_SDAM_A16_IS_A5		|\			 PSDMR_BSMA_A15_A17		|\			 PSDMR_SDA10_PBI1_A6		|\			 PSDMR_RFRC_7_CLK		|\			 PSDMR_PRETOACT_3W		|\			 PSDMR_ACTTORW_2W		|\			 PSDMR_LDOTOPRE_1C		|\			 PSDMR_WRC_1C			|\			 PSDMR_CL_2)/* * Init Memory Controller: * * Bank Bus     Machine PortSz  Device * ---- ---     ------- ------  ------ *  0   60x     GPCM    8  bit  Boot ROM *  1   60x     GPCM    64 bit  FLASH *  2   60x     SDRAM   64 bit  SDRAM * */#define CFG_MRS_OFFS	0x00000000/* Bank 0 - FLASH */#define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\			 BRx_PS_16                      |\			 BRx_MS_GPCM_P                  |\			 BRx_V)#define CFG_OR0_PRELIM  (P2SZ_TO_AM(CFG_FLASH_SIZE)     |\			 ORxG_CSNT                      |\			 ORxG_ACS_DIV1                  |\			 ORxG_SCY_3_CLK                 |\			 ORxU_EHTR_8IDLE)/* Bank 2 - 60x bus SDRAM */#ifndef CFG_RAMBOOT#define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\			 BRx_PS_64                      |\			 BRx_MS_SDRAM_P                 |\			 BRx_V)#define CFG_OR2_PRELIM	 CFG_OR2_8COL#define CFG_PSDMR	 CFG_PSDMR_8COL#endif /* CFG_RAMBOOT */#define CFG_BR4_PRELIM  ((RTC_BASE_ADDR & BRx_BA_MSK)   |\			 BRx_PS_8                       |\			 BRx_MS_UPMA                    |\			 BRx_V)#define CFG_OR4_PRELIM  (ORxU_AM_MSK | ORxU_BI)/*----------------------------------------------------------------------- * PCMCIA stuff *----------------------------------------------------------------------- * */#define CONFIG_I82365#define CFG_PCMCIA_MEM_ADDR	0x81000000#define CFG_PCMCIA_MEM_SIZE	0x1000/*----------------------------------------------------------------------- * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) *----------------------------------------------------------------------- */#define CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card Adapter */#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE	 not supported	*/#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/#define CFG_ATA_IDE0_OFFSET	0x0000#define CFG_ATA_BASE_ADDR	0xa0000000/* Offset for data I/O			*/#define CFG_ATA_DATA_OFFSET	0x100/* Offset for normal register accesses	*/#define CFG_ATA_REG_OFFSET	0x100/* Offset for alternate registers	*/#define CFG_ATA_ALT_OFFSET	0x108#endif	/* __CONFIG_H */