*/#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux *//*----------------------------------------------------------------------- * FLASH organization */#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot *//*----------------------------------------------------------------------- * Cache Configuration */#define CFG_DCACHE_SIZE		0x4000	/* For IBM 405GPr CPUs			*/#define CFG_CACHELINE_SIZE	32	/* ...			*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/#endif/*----------------------------------------------------------------------- * Logbuffer Configuration */#undef CONFIG_LOGBUFFER 	/* supported but not enabled *//*----------------------------------------------------------------------- * Bootcountlimit Configuration */#undef CONFIG_BOOTCOUNT_LIMIT	/* supported but not enabled *//*----------------------------------------------------------------------- * POST Configuration */#if 0 /* enable this if POST is desired (is supported but not enabled) */#define CONFIG_POST		(CFG_POST_MEMORY	| \				 CFG_POST_CPU 		| \				 CFG_POST_RTC 		| \				 CFG_POST_I2C)#endif/* * Init Memory Controller: */#define FLASH_MAX_SIZE		0x00800000		/* 8MByte max */#define FLASH_BASE_PRELIM	0xFF800000  /* open the flash CS *//* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */#define FLASH_SIZE_PRELIM	 3  /* maximal flash FLASH size bank #0	*/#define CONFIG_BOARD_EARLY_INIT_F 1/* Peripheral Bus Mapping */#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000#define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */#define CFG_TEMP_STACK_OCM      1#define CFG_OCM_DATA_ADDR	0xF0000000#define CFG_OCM_DATA_SIZE	0x1000#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)/* reserve some memory for POST and BOOT limit info */#define CFG_INIT_SP_OFFSET	(CFG_GBL_DATA_OFFSET - 32)#ifdef  CONFIG_POST		/* reserve one word for POST Info */#define CFG_POST_WORD_ADDR	(CFG_GBL_DATA_OFFSET - 4)#endif#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 12)#endif/* * Internal Definitions * * Boot Flags */#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*//*********************************************************************** * External peripheral base address ***********************************************************************/#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000/*********************************************************************** * Last Stage Init ***********************************************************************/#define CONFIG_LAST_STAGE_INIT/************************************************************ * Ethernet Stuff ***********************************************************/#define CONFIG_MII		1	/* MII PHY management		*/#define CONFIG_PHY_ADDR		1	/* PHY address			*/#define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */#define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this *//************************************************************ * RTC ***********************************************************/#define CONFIG_RTC_MC146818#undef CONFIG_WATCHDOG			/* watchdog disabled		*//************************************************************ * IDE/ATA stuff ************************************************************/#if defined(CONFIG_MIP405T)#define CFG_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/#else#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/#endif#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */#define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */#define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/#define CFG_ATA_REG_OFFSET 	0		/* reg offset */#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */#undef	CONFIG_IDE_LED	       /* no led for ide supported     */#define CONFIG_IDE_RESET       /* reset for ide supported...	*/#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */#define CONFIG_SUPPORT_VFAT/************************************************************ * ATAPI support (experimental) ************************************************************/#define CONFIG_ATAPI			/* enable ATAPI Support *//************************************************************ * SCSI support (experimental) only SYM53C8xx supported ************************************************************/#undef CONFIG_SCSI_SYM53C8XX#ifdef CONFIG_SCSI_SYM53C8XX#define CFG_SCSI_MAX_LUN	8 /* number of supported LUNs */#define CFG_SCSI_MAX_SCSI_ID	7 /* maximum SCSI ID (0..6) */#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */#define CFG_SCSI_SPIN_UP_TIME	2#endif /* CONFIG_SCSI_SYM53C8XX *//************************************************************ * DISK Partition support ************************************************************/#define CONFIG_DOS_PARTITION#define CONFIG_MAC_PARTITION#define CONFIG_ISO_PARTITION /* Experimental *//************************************************************ * Disk-On-Chip configuration ************************************************************/#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/#define CFG_DOC_SHORT_TIMEOUT#define CFG_DOC_SUPPORT_2000#define CFG_DOC_SUPPORT_MILLENNIUM/************************************************************ * Keyboard support ************************************************************/#undef CONFIG_ISA_KEYBOARD/************************************************************ * Video support ************************************************************/#define CONFIG_VIDEO			/*To enable video controller support */#define CONFIG_VIDEO_CT69000#define CONFIG_CFB_CONSOLE#define CONFIG_VIDEO_LOGO#define CONFIG_CONSOLE_EXTRA_INFO#define CONFIG_VGA_AS_SINGLE_DEVICE#define CONFIG_VIDEO_SW_CURSOR#undef CONFIG_VIDEO_ONBOARD/************************************************************ * USB support EXPERIMENTAL ************************************************************/#if !defined(CONFIG_MIP405T)#define CONFIG_USB_UHCI#define CONFIG_USB_KEYBOARD#define CONFIG_USB_STORAGE/* Enable needed helper functions */#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */#endif/************************************************************ * Debug support ************************************************************/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */#endif/************************************************************ * support BZIP2 compression ************************************************************/#define CONFIG_BZIP2		1/************************************************************ * Ident ************************************************************/#define VERSION_TAG "released"#if !defined(CONFIG_MIP405T)#define CONFIG_ISO_STRING "MEV-10072-001"#else#define CONFIG_ISO_STRING "MEV-10082-001"#endif#if !defined(CONFIG_BOOT_PCI)#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG#else#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"#endif#endif	/* __CONFIG_H */