/* * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA *//* * board/config.h - configuration options, board specific */#ifndef __CONFIG_H#define __CONFIG_H/* * Workaround for layout bug on prototype board */#define	PCU_E_WITH_SWAPPED_CS	1/* * High Level Configuration Options * (easy to change) */#define CONFIG_MPC860		1	/* This is a MPC860T CPU	*/#define CONFIG_MPC860T		1#define CONFIG_PCU_E		1	/* ...on a PCU E board		*/#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/#define CONFIG_BAUDRATE		9600#if 0#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/#else#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/#endif#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */#undef	CONFIG_BOOTARGS#define CONFIG_BOOTCOMMAND							\	"bootp;"								\	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"	\	"bootm"#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/#define	CONFIG_PRAM		2048	/* reserve 2 MB "protected RAM"	*/#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/#define	CONFIG_SPI			/* enable SPI driver		*/#define	CONFIG_SPI_X			/* 16 bit EEPROM addressing	*/#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/#define CFG_I2C_SLAVE		0x7F/* ---------------------------------------------------------------- * Offset to initial SPI buffers in DPRAM (used if the environment * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to * use at an early stage. It is used between the two initialization * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it * far enough from the start of the data area (as well as from the * stack pointer). * ---------------------------------------------------------------- */#define CFG_SPI_INIT_OFFSET		0xB00#define CONFIG_COMMANDS		(	CONFIG_CMD_DFL	| \					CFG_CMD_DATE	| \					CFG_CMD_EEPROM	| \					CFG_CMD_BSP	)#define CONFIG_BOOTP_MASK \    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */#include <cmd_confdefs.h>/*----------------------------------------------------------------------*//* * Miscellaneous configurable options */#define	CFG_LONGHELP			/* undef to save memory		*/#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/#if (CONFIG_COMMANDS & CFG_CMD_KGDB)#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/#else#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/#endif#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */#define	CFG_MAXARGS	16		/* max number of command args	*/#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/#define CFG_MEMTEST_START	0x00100000	/* memtest works on	*/#define CFG_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/#define	CFG_LOAD_ADDR		0x00100000	/* default load address	*/#define	CFG_PIO_MODE		0	/* IDE interface in PIO Mode 0	*//* Ethernet hardware configuration done using port pins */#define CFG_PB_ETH_RESET	0x00000020		/* PB 26	*/#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_PA_ETH_MDDIS	0x4000			/* PA  1	*/#define CFG_PB_ETH_POWERDOWN	0x00000800		/* PB 20	*/#define CFG_PB_ETH_CFG1		0x00000400		/* PB 21	*/#define CFG_PB_ETH_CFG2		0x00000200		/* PB 22	*/#define CFG_PB_ETH_CFG3		0x00000100		/* PB 23	*/#else /* XXX */#define CFG_PB_ETH_MDDIS	0x00000010		/* PB 27	*/#define CFG_PB_ETH_POWERDOWN	0x00000100		/* PB 23	*/#define CFG_PB_ETH_CFG1		0x00000200		/* PB 22	*/#define CFG_PB_ETH_CFG2		0x00000400		/* PB 21	*/#define CFG_PB_ETH_CFG3		0x00000800		/* PB 20	*/#endif /* XXX *//* Ethernet settings: * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex */#define CFG_ETH_MDDIS_VALUE	0#define CFG_ETH_CFG1_VALUE	1#define CFG_ETH_CFG2_VALUE	1#define CFG_ETH_CFG3_VALUE	1/* PUMA configuration */#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_PB_PUMA_PROG	0x00000010		/* PB 27	*/#else /* XXX */#define CFG_PA_PUMA_PROG	0x4000			/* PA  1	*/#endif /* XXX */#define CFG_PC_PUMA_DONE	0x0008			/* PC 12	*/#define CFG_PC_PUMA_INIT	0x0004			/* PC 13	*/#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }/* * Low Level Configuration Settings * (address mappings, register initial values, etc.) * You should know what you are doing if you make changes here. *//*----------------------------------------------------------------------- * Internal Memory Mapped Register */#define CFG_IMMR		0xFE000000/*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in DPRAM) */#define CFG_INIT_RAM_ADDR	CFG_IMMR#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET/*----------------------------------------------------------------------- * Address accessed to reset the board - must not be mapped/assigned */#define	CFG_RESET_ADDRESS	0xFEFFFFFF/*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */#define	CFG_SDRAM_BASE		0x00000000/* this is an ugly hack needed because of the silly non-constant address map */#define CFG_FLASH_BASE		(0-flash_info[0].size-flash_info[1].size)#if defined(DEBUG)#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/#else#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/#endif#define CFG_MONITOR_BASE	TEXT_BASE#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*//* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*//*----------------------------------------------------------------------- * FLASH organization */#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/#define CFG_MAX_FLASH_SECT	160	/* max number of sectors on one chip	*/#define CFG_FLASH_ERASE_TOUT	180000	/* Timeout for Flash Erase (in ms)	*/#define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/#if 0/* Start port with environment in flash; switch to SPI EEPROM later */#define	CFG_ENV_IS_IN_FLASH	1#define CFG_ENV_SIZE		0x2000	/* Total Size of Environment 		*/#define CFG_ENV_ADDR	    0xFFFFE000	/* Address    of Environment Sector	*/#define CFG_ENV_SECT_SIZE	0x2000	/* use the top-most 8k boot sector	*/#else/* Final version: environment in EEPROM */#define CFG_ENV_IS_IN_EEPROM	1#define CFG_I2C_EEPROM_ADDR	0#define CFG_I2C_EEPROM_ADDR_LEN	2#define CFG_ENV_OFFSET		1024#define CFG_ENV_SIZE		1024#endif/*----------------------------------------------------------------------- * Cache Configuration */#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*//*----------------------------------------------------------------------- * SYPCR - System Protection Control				11-9 * SYPCR can only be written once after reset! *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */#if defined(CONFIG_WATCHDOG)#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)#else#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)#endif/*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration				11-6 *----------------------------------------------------------------------- * External Arbitration max. priority (7), * Debug pins configuration '11', * Asynchronous external master enable. *//* => 0x70600200 */#define CFG_SIUMCR	(SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)/*----------------------------------------------------------------------- * TBSCR - Time Base Status and Control				11-26 *----------------------------------------------------------------------- * Clear Reference Interrupt Status, Timebase freezing enabled */#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)