/*----------------------------------------------------------------------- * PISCR - Periodic Interrupt Status and Control		11-31 *----------------------------------------------------------------------- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled */#define CFG_PISCR	(PISCR_PS | PISCR_PITF)/*----------------------------------------------------------------------- * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30 *----------------------------------------------------------------------- * Reset PLL lock status sticky bit, timer expired status bit and timer * interrupt status bit, set PLL multiplication factor ! *//* 0x00004080 */#define	CFG_PLPRCR_MF	0	/* (0+1) * 50 = 50 MHz Clock */#define CFG_PLPRCR							\		(	(CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |		\			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |	\			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\			PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/	\		)#define	CONFIG_8xx_GCLK_FREQ	((CFG_PLPRCR_MF+1)*50000000)/*----------------------------------------------------------------------- * SCCR - System Clock and reset Control Register		15-27 *----------------------------------------------------------------------- * Set clock output, timebase and RTC source and divider, * power management and some other internal clocks * * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz */#define SCCR_MASK	SCCR_EBDF11/* 0x01800000 */#define CFG_SCCR	(SCCR_COM00	| /*SCCR_TBS|*/		\			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/ 	\			 SCCR_EBDF00 |   SCCR_DFSYNC00 |	\			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\			 SCCR_DFNH000	|   SCCR_DFLCD100 |	\			 SCCR_DFALCD01)/*----------------------------------------------------------------------- * RTCSC - Real-Time Clock Status and Control Register		11-27 *----------------------------------------------------------------------- * * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!! * * Don't expect the "date" command to work without a 32kHz clock input! *//* 0x00C3 => 0x0003 */#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)/*----------------------------------------------------------------------- * RCCR - RISC Controller Configuration Register		19-4 *----------------------------------------------------------------------- */#define CFG_RCCR 0x0000/*----------------------------------------------------------------------- * RMDS - RISC Microcode Development Support Control Register *----------------------------------------------------------------------- */#define CFG_RMDS 0/*----------------------------------------------------------------------- * * Interrupt Levels *----------------------------------------------------------------------- */#define CFG_CPM_INTERRUPT	13	/* SIU_LEVEL6	*//*----------------------------------------------------------------------- * *----------------------------------------------------------------------- * */#define CFG_DER	0/* * Init Memory Controller: * * BR0/1 and OR0/1 (FLASH) - second Flash bank optional */#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/#if PCU_E_WITH_SWAPPED_CS /* XXX */#define FLASH_BASE6_PRELIM	0xFF000000	/* FLASH bank #1	*/#else /* XXX */#define FLASH_BASE1_PRELIM	0xFF000000	/* FLASH bank #1	*/#endif /* XXX *//* * used to re-map FLASH: restrict access enough but not too much to * meddle with FLASH accesses */#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask *//* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1			*/#define CFG_OR_TIMING_FLASH	(OR_SCY_8_CLK | OR_EHTR)#define CFG_OR0_REMAP	( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \				CFG_OR_TIMING_FLASH)#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \				CFG_OR_TIMING_FLASH)/* 16 bit, bank valid */#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_OR6_REMAP	CFG_OR0_REMAP#define CFG_OR6_PRELIM	CFG_OR0_PRELIM#define CFG_BR6_PRELIM	((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )#else /* XXX */#define CFG_OR1_REMAP	CFG_OR0_REMAP#define CFG_OR1_PRELIM	CFG_OR0_PRELIM#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )#endif /* XXX *//* * BR2/OR2: SDRAM * * Multiplexed addresses, GPL5 output to GPL5_A (don't care) */#if PCU_E_WITH_SWAPPED_CS /* XXX */#define SDRAM_BASE5_PRELIM	0x00000000	/* SDRAM bank */#else /* XXX */#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank */#endif /* XXX */#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map 128 MB (>SDRAM_MAX_SIZE!) */#define SDRAM_TIMING		OR_CSNT_SAM	/* SDRAM-Timing */#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_OR5_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )#define CFG_BR5_PRELIM	((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )#else /* XXX */#define CFG_OR2_PRELIM	(SDRAM_PRELIM_OR_AM | SDRAM_TIMING )#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )#endif /* XXX *//* * BR3/OR3: CAN Controller *	BR3: 0x10000401		OR3: 0xffff818a */#define CAN_CTRLR_BASE		0x10000000	/* CAN Controller */#define CAN_CTRLR_OR_AM		0xFFFF8000	/* 32 kB */#define CAN_CTRLR_TIMING	(OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_BR4_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)#define CFG_OR4_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)#else /* XXX */#define CFG_BR3_PRELIM		((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)#define CFG_OR3_PRELIM		(CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)#endif /* XXX *//* * BR4/OR4: PUMA Config * * Memory controller will be used in 2 modes: * * - "read" mode: *	BR4: 0x10100801		OR4: 0xffff8530 * - "load" mode (chip select on UPM B): *	BR4: 0x101008c1		OR4: 0xffff8630 * * Default initialization is in "read" mode */#define PUMA_CONF_BASE		0x10100000	/* PUMA Config */#define PUMA_CONF_OR_AM		0xFFFF8000	/* 32 kB */#define	PUMA_CONF_LOAD_TIMING	(OR_ACS_DIV2	 | OR_SCY_3_CLK)#define PUMA_CONF_READ_TIMING	(OR_G5LA | OR_BI | OR_SCY_3_CLK)#define PUMA_CONF_BR_LOAD	((PUMA_CONF_BASE & BR_BA_MSK) | \					BR_PS_16 | BR_MS_UPMB | BR_V)#define PUMA_CONF_OR_LOAD	(PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)#define PUMA_CONF_BR_READ	((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)#define PUMA_CONF_OR_READ	(PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_BR3_PRELIM		PUMA_CONF_BR_READ#define CFG_OR3_PRELIM		PUMA_CONF_OR_READ#else /* XXX */#define CFG_BR4_PRELIM		PUMA_CONF_BR_READ#define CFG_OR4_PRELIM		PUMA_CONF_OR_READ#endif /* XXX *//* * BR5/OR5: PUMA: SMA Bus 8 Bit *	BR5: 0x10200401		OR5: 0xffe0010a */#define PUMA_SMA8_BASE		0x10200000	/* PUMA SMA Bus 8 Bit */#define PUMA_SMA8_OR_AM		0xFFE00000	/* 2 MB */#define PUMA_SMA8_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_BR2_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)#define CFG_OR2_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)#else /* XXX */#define CFG_BR5_PRELIM		((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)#define CFG_OR5_PRELIM		(PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)#endif /* XXX *//* * BR6/OR6: PUMA: SMA Bus 16 Bit *	BR6: 0x10600801		OR6: 0xffe0010a */#define PUMA_SMA16_BASE		0x10600000	/* PUMA SMA Bus 16 Bit */#define PUMA_SMA16_OR_AM	0xFFE00000	/* 2 MB */#define PUMA_SMA16_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)#if PCU_E_WITH_SWAPPED_CS /* XXX */#define CFG_BR1_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)#define CFG_OR1_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)#else /* XXX */#define CFG_BR6_PRELIM		((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)#define CFG_OR6_PRELIM		(PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)#endif /* XXX *//* * BR7/OR7: PUMA: external Flash *	BR7: 0x10a00801		OR7: 0xfe00010a */#define PUMA_FLASH_BASE		0x10A00000	/* PUMA external Flash */#define PUMA_FLASH_OR_AM	0xFE000000	/* 32 MB */#define PUMA_FLASH_TIMING	(OR_BI | OR_SCY_0_CLK | OR_EHTR)#define CFG_BR7_PRELIM		((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)#define CFG_OR7_PRELIM		(PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)/* * Memory Periodic Timer Prescaler *//* periodic timer for refresh */#define CFG_MPTPR	0x0200/* * MAMR settings for SDRAM * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10, *		MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X *//* periodic timer for refresh */#define CFG_MAMR_PTA	0x30	/* = 48 */#define CFG_MAMR	( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \			  MAMR_AMA_TYPE_1	| \			  MAMR_G0CLA_A10	| \			  MAMR_RLFA_1X		| \			  MAMR_WLFA_1X		| \			  MAMR_TLFA_8X		)/* * Internal Definitions * * Boot Flags */#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/#define BOOTFLAG_WARM	0x02		/* Software reboot			*/#endif	/* __CONFIG_H */