/* * (C) Copyright 2003, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt@psyent.com> * Stephan Linz <linz@li-pro.net> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#ifndef __CONFIG_H#define __CONFIG_H/*********************************************************************** * Include the whole NIOS CPU configuration. * * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!! * ***********************************************************************/#if	defined(CONFIG_NIOS_SAFE_32)#include <configs/DK1C20_safe_32.h>#elif	defined(CONFIG_NIOS_STANDARD_32)#include <configs/DK1C20_standard_32.h>#else#error *** CFG_ERROR: you have to setup right NIOS CPU configuration#endif/*------------------------------------------------------------------------ * BOARD/CPU -- TOP-LEVEL *----------------------------------------------------------------------*/#define CONFIG_NIOS		1		/* NIOS-32 core		*/#define	CONFIG_DK1C20		1		/* Cyclone DK-1C20 board*/#define CONFIG_SYS_CLK_FREQ	CFG_NIOS_CPU_CLK/* 50 MHz core clock	*/#define	CFG_HZ			1000		/* 1 msec time tick	*/#undef  CFG_CLKS_IN_HZ#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*//*------------------------------------------------------------------------ * BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM) *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_SDRAM_SIZE != 0)#define CFG_SDRAM_BASE		CFG_NIOS_CPU_SDRAM_BASE#define CFG_SDRAM_SIZE		CFG_NIOS_CPU_SDRAM_SIZE#else#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config#endif#define CFG_SRAM_BASE		CFG_NIOS_CPU_SRAM_BASE#define CFG_SRAM_SIZE		CFG_NIOS_CPU_SRAM_SIZE#define CFG_VECT_BASE		CFG_NIOS_CPU_VEC_BASE/*------------------------------------------------------------------------ * MEMORY ORGANIZATION - For the most part, you can put things pretty * much anywhere. This is pretty flexible for Nios. So here we make some * arbitrary choices & assume that the monitor is placed at the end of * a memory resource (so you must make sure TEXT_BASE is chosen * appropriately). * * 	-The heap is placed below the monitor. * 	-Global data is placed below the heap. * 	-The stack is placed below global data (&grows down). *----------------------------------------------------------------------*/#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/#define CFG_GBL_DATA_SIZE	128		/* Global data size rsvd*/#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128*1024)#define CFG_MONITOR_BASE	TEXT_BASE#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)#define CFG_GBL_DATA_OFFSET	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)#define CFG_INIT_SP		CFG_GBL_DATA_OFFSET/*------------------------------------------------------------------------ * FLASH (AM29LV065D) *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)#define CFG_FLASH_BASE		CFG_NIOS_CPU_FLASH_BASE#define CFG_FLASH_SIZE		CFG_NIOS_CPU_FLASH_SIZE#define CFG_MAX_FLASH_SECT	128		/* Max # sects per bank */#define CFG_MAX_FLASH_BANKS	1		/* Max # of flash banks */#define CFG_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */#define CFG_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */#define CFG_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/#else#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config#endif/*------------------------------------------------------------------------ * ENVIRONMENT *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_FLASH_SIZE != 0)#define	CFG_ENV_IS_IN_FLASH	1		/* Environment in flash */#define CFG_ENV_ADDR		CFG_FLASH_BASE	/* Mem addr of env	*/#define CFG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/#define CONFIG_ENV_OVERWRITE			/* Serial/eth change Ok */#else#define	CFG_ENV_IS_NOWHERE	1		/* NO Environment	*/#endif/*------------------------------------------------------------------------ * CONSOLE *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_UART_NUMS != 0)#define CFG_NIOS_CONSOLE	CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */#if	(CFG_NIOS_CPU_UART0_BR != 0)#define CFG_NIOS_FIXEDBAUD	1		   /* Baudrate is fixed	*/#define CONFIG_BAUDRATE		CFG_NIOS_CPU_UART0_BR#else#undef	CFG_NIOS_FIXEDBAUD#define CONFIG_BAUDRATE		115200#endif#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }#else#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config#endif/*------------------------------------------------------------------------ * TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc  PIT, * so an avalon bus timer is required. *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_TIMER_NUMS != 0)#if	(CFG_NIOS_CPU_TICK_TIMER == 0)#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick	*/#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER0_IRQ#if	(CFG_NIOS_CPU_TIMER0_FP == 1)		    /* fixed period */#if	(CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)#else#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ#endif#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */#elif	(CFG_NIOS_CPU_TIMER0_FP == 0)		    /* variable period */#if	(CFG_HZ <= 1000)#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)#else#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000#endif#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)#else#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct#endif#elif	(CFG_NIOS_CPU_TICK_TIMER == 1)#define CFG_NIOS_TMRBASE	CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick	*/#define CFG_NIOS_TMRIRQ		CFG_NIOS_CPU_TIMER1_IRQ#if	(CFG_NIOS_CPU_TIMER1_FP == 1)		    /* fixed period */#if	(CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)#define CFG_NIOS_TMRMS		(CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)#else#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ#endif#undef	CFG_NIOS_TMRCNT	/* no preloadable counter value */#elif	(CFG_NIOS_CPU_TIMER1_FP == 0)		    /* variable period */#if	(CFG_HZ <= 1000)#define CFG_NIOS_TMRMS		(1000 / CFG_HZ)#else#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000#endif#define	CFG_NIOS_TMRCNT		(CONFIG_SYS_CLK_FREQ / CFG_HZ)#else#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct#endif#endif	/* CFG_NIOS_CPU_TICK_TIMER */#else#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config#endif/*------------------------------------------------------------------------ * Ethernet *----------------------------------------------------------------------*/#if	(CFG_NIOS_CPU_LAN_NUMS == 1)#if	(CFG_NIOS_CPU_LAN0_TYPE == 0)		/* LAN91C111		*/#define	CONFIG_DRIVER_SMC91111			/* Using SMC91c111	*/#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/#define	CONFIG_SMC91111_BASE	(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)#define	CONFIG_SMC_USE_32_BIT	1#else	/* no */#undef	CONFIG_SMC_USE_32_BIT#endif#elif	(CFG_NIOS_CPU_LAN0_TYPE == 1)		/* CS8900A		*/	/********************************************/	/* !!! CS8900 is __not__ tested on NIOS !!! */	/********************************************/#define	CONFIG_DRIVER_CS8900			/* Using CS8900		*/#define	CS8900_BASE		(CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)#if	(CFG_NIOS_CPU_LAN0_BUSW == 32)#undef	CS8900_BUS16#define	CS8900_BUS32		1#else	/* no */#define	CS8900_BUS16		1#undef	CS8900_BUS32#endif#else#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config#endif#define CONFIG_ETHADDR		08:00:3e:26:0a:5b#define CONFIG_NETMASK		255.255.255.0#define CONFIG_IPADDR		192.168.2.21#define CONFIG_SERVERIP		192.168.2.16#else#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h#endif/*------------------------------------------------------------------------ * STATUS LEDs